VHDL-FPGA-Verilog List Page 45

VHDL-FPGA-Verilog list

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4bit_moore Downloaded：0: Moore machine is state machine whose output is a function of only the current state.
Date : 2025-06-26 Size : 6kb User : liki20
HDL_equation Downloaded：0: Verilog Program to implement the function f=x+yz and Testbench for all the possible inputs using For Loop
Date : 2025-06-26 Size : 5kb User : liki20
16_COMLEX ADDER Downloaded：0: Complex Numbers are denoted in the form a+ib where a is the real part and b is the imaginary part
Date : 2025-06-26 Size : 5kb User : liki20
4位全加器计数器等程序 Downloaded：0: EDA simulation tools used for EDA development of multiple programs; Including: 4 bit full adder, 12 frequency division, 128 frequency division, basketball counting stopwatch (part), counter; It can be used with EDA simul
Date : 2025-06-26 Size : 1kb User : 李云龙777
FPGA_flash设计 Downloaded：0: Our design uses a FSM controller to control what commands are sent. The flash module judges the state signal sent by the FSM to select what operation should be performed. When the command is written or read out, a flag_d
Date : 2025-06-26 Size : 244kb User : 硅渣渣
FPGA_USB2.0设计 Downloaded：0: The FX2 is configured from FIFO mode, configured as MCU working clock 24M, endpoint 2 output, byte 1024, endpoint 6 input, byte 1024, signal all set to low level and so on. Our module drive clock is configured as an inte
Date : 2025-06-26 Size : 420kb User : 硅渣渣
FPGA_实时时钟设计 Downloaded：0: By configuring DS1302 chip to monitor the real-time clock, we select the time that we want to display on the digital tube by controlling 2 keys. Press key 1 to show the week, press the key 2 to show the year and month, n
Date : 2025-06-26 Size : 348kb User : 硅渣渣
FPGA_红外遥控系统设计 Downloaded：0: After power up, our design will send a given data code, then the receiving module will accept the data that it sends and display it on the digital tube. Then we can use our remote control keyboard to send the data, the r
Date : 2025-06-26 Size : 426kb User : 硅渣渣
JY901 Downloaded：0: usart Ustartled control code for test use, P10 unit available
Date : 2025-06-26 Size : 4kb User : 田联合
fpga Downloaded：0: Implementation of FFT on FPGA 1. the implementation of 1024 point FFT algorithm based on FPGA; 2. the design and implementation of FFT algorithm based on FPGA; 3. design and implementation of a variable point FFT process
Date : 2025-06-26 Size : 18.01mb User : wsf-jv
各种密码算法的FPGA实现情况 Downloaded：0: FPGA implementation of various cryptographic algorithms
Date : 2025-06-26 Size : 17.08mb User : wsf-jv
fft_32k Downloaded：0: FFT 32K Point Design Example v1.0.0 README File This readme file for the Fast Fourier Transform (FFT) 32K Point Design contains information about the design example posted on the Altera Support website: http://www.altera
Date : 2025-06-26 Size : 1.07mb User : wsf-jv

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