VHDL-FPGA-Verilog List Page 50

VHDL-FPGA-Verilog list

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proj Downloaded：0: BCH coding and decoding of 15.k, thesis, project
Date : 2025-06-26 Size : 81kb User : zhou9619
control_tube Downloaded：0: Define the LX6 series pin and implement the timer,
Date : 2025-06-26 Size : 375kb User : VVDD
car_detect Downloaded：0: The number of vehicles in the parking lot can be obtained by detecting and recording vehicle entry and exit.
Date : 2025-06-26 Size : 39kb User : 小明与小明
key_jitter_decade_counter_seg Downloaded：0: We use the recording of the jitter time to achieve the key dithering and record the number of keys.
Date : 2025-06-26 Size : 63kb User : 小明与小明
posedge_detect Downloaded：0: The enabling signal is often a pulse. This program realizes the detection of the enabling signal
Date : 2025-06-26 Size : 72kb User : 小明与小明
cnt4M Downloaded：0: 50M frequency divider
Date : 2025-06-26 Size : 1.54mb User : xidianstudent
Verilog数字系统设计教程(第二版) 夏宇闻 Downloaded：0: A good tool book for Verilog language learning
Date : 2025-06-26 Size : 6.81mb User : 走吧_hit
handshack Downloaded：0: Hold the simulation of mobile phone system, open with ISE14.7, Modelsim se6.5.
Date : 2025-06-26 Size : 69kb User : 阿士大夫
dds Downloaded：0: DDS algorithm, call Xilinx IP, ISE
Date : 2025-06-26 Size : 5.46mb User : 阿士大夫
FPGA教程 Downloaded：0: FPGA programming skills, very good
Date : 2025-06-26 Size : 10.78mb User : bh_hh
SPI Downloaded：0: Using Verilog language to realize FPGA serial communication
Date : 2025-06-26 Size : 15kb User : 柠檬琉璃夏
aes256 Downloaded：0: AES256 encryption based on FPGA,according to AES128 bit encryption.There are still some problems to be improved.
Date : 2025-06-26 Size : 19kb User : Echo000

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