VHDL-FPGA-Verilog List Page 3264

VHDL-FPGA-Verilog list

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lcd Downloaded：0: In and Jones SEED-XDTK platform, based on XC4Vsx25 liquid crystal driver.
Date : 2025-07-22 Size : 761kb User : hechao
key Downloaded：0: In and Jones SEED-XDTK platform, based on the key scan XC4Vsx25 driver.
Date : 2025-07-22 Size : 501kb User : hechao
parall_ad_da Downloaded：0: In and Jones SEED-XDTK platform, based on the parallel XC4VSX25 modulus, digital-analog conversion process
Date : 2025-07-22 Size : 801kb User : hechao
GenDEC.RTL Downloaded：0: Tristate Bus Tristate Bus
Date : 2025-07-22 Size : 2kb User : tsingyuanlee
div7 Downloaded：0: DIV7 circle
Date : 2025-07-22 Size : 1kb User : 张强
ss Downloaded：0: thanks you
Date : 2025-07-22 Size : 1kb User : 张强
16_bits_CPU_verilog_code Downloaded：0: the example of 16 bits CPU using verilog
Date : 2025-07-22 Size : 860kb User : 王惠娟
emny Downloaded：0: cpld/fpga vhdl language rom cited a simple example
Date : 2025-07-22 Size : 391kb User : chen
t51 Downloaded：0: VHDL design with a rounded judge circuit, its input 8421BCD code require that when the input is greater than or equal to 5 and less than 10, the discrimination circuit output is 1, less than 5 to 0, greater than or equal
Date : 2025-07-22 Size : 1kb User : hualiayue
LED7s Downloaded：0: Written in VHDL language with the LED seven-segment display decoder
Date : 2025-07-22 Size : 1kb User : hualiayue
hanzi1 Downloaded：0: Written in VHDL, the crystal lattice display Chinese characters of the program
Date : 2025-07-22 Size : 5kb User : hualiayue
codelock Downloaded：0: Design a simple digital electronic locks, password 4. Function: 1, the password input: Each press of a button, requiring digital tube display, and turn left 2, password clear: clear the password input, and will enter the
Date : 2025-07-22 Size : 502kb User : hualiayue

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