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VHDL-FPGA-Verilog list
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shouhuoji
Downloaded:0
Use a text methodology for the preparation of the vhdl code for a vending machine
Date
: 2025-07-22
Size
: 35kb
User
:
小陈
xuliejianceqi
Downloaded:0
vhdl prepared by the sequence detectors, including the module, as well as the top-level document
Date
: 2025-07-22
Size
: 292kb
User
:
小陈
dds
Downloaded:0
Dds with vhdk signal generator written in code, using fpga implementation dds feature
Date
: 2025-07-22
Size
: 363kb
User
:
小陈
DE2_i2sound
Downloaded:0
FPGA-based audio signal A/D conversion, for DE2 development board.
Date
: 2025-07-22
Size
: 34kb
User
:
wendy
symbolic_decomposition
Downloaded:0
symbolic_decomposition
Date
: 2025-07-22
Size
: 2.55mb
User
:
wangyang
edaok_UART_FPGA
Downloaded:0
With the FPGA to achieve UART serial communication, you can set the data bits, parity bit, parity, etc.
Date
: 2025-07-22
Size
: 3.94mb
User
:
杨奔
EDA
Downloaded:0
The above information is on the FPGA chip and the hardware link diagram, on the development of FPGA a very important role. There are a number of related software programs for reference
Date
: 2025-07-22
Size
: 7.8mb
User
:
神老板
fw
Downloaded:0
one hot state machine.. is the project name. this is a file to execute in vhdl... it is very useful in many applications, just hav a look guys.
Date
: 2025-07-22
Size
: 276kb
User
:
mythu
SDRAMverilog
Downloaded:0
SDRAM-driven, Verilog HDL source code
Date
: 2025-07-22
Size
: 291kb
User
:
刘越
keyscan
Downloaded:0
verilog code written keyscan, reproduced, and for them to learn about! Thanks
Date
: 2025-07-22
Size
: 1kb
User
:
袁科学
clock_generator
Downloaded:0
clock generator verilog code for your reference
Date
: 2025-07-22
Size
: 160kb
User
:
袁科学
data_interleaver
Downloaded:0
Verlog coded data interleaving code, want to help everyone
Date
: 2025-07-22
Size
: 231kb
User
:
袁科学
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