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CyclonePLL
Downloaded:0
Cyclone ™ FPGA with a phase-locked loop (PLL) and the global clock network and provide a complete clock management solution. Cyclone PLL with the clock multiplier and divider, phase offset, programmable duty cycle a
Date
: 2025-07-22
Size
: 541kb
User
:
裴雷
61EDA_D888
Downloaded:0
Based on Verilog HDL Taxi Accounting System
Date
: 2025-07-22
Size
: 416kb
User
:
panda chen
DES-HDL
Downloaded:0
HDL implementation of the DES with the encryption algorithm, by pre-simulation, we want to help
Date
: 2025-07-22
Size
: 27kb
User
:
su
Cymometer
Downloaded:0
Written in Verilog frequency counter, using 8-bit LED as the display, Quartus II 6.0 of the project file. To ensure easy to use, EPM240T chips. 66 of the resources used.
Date
: 2025-07-22
Size
: 572kb
User
:
石头
VHDL
Downloaded:0
VHDL language design with seven-segment display decoder
Date
: 2025-07-22
Size
: 1kb
User
:
冷与
lock
Downloaded:0
Design an 8-bit serial digital code lock control circuit
Date
: 2025-07-22
Size
: 1kb
User
:
冷与
vhdl
Downloaded:0
Responder a vhdl design
Date
: 2025-07-22
Size
: 1kb
User
:
冷与
DSP_FIR_Lab
Downloaded:0
This is DSP FIR lab, it includes there forms to implement FIR, direct form, transposed form and time mulitple form, all code has been tested on Modesim.
Date
: 2025-07-22
Size
: 7kb
User
:
hongwan
DISPLAYS_FINAL
Downloaded:0
Program in VHDL. Developed for the spartan 3 kit. It is composed of 4-bit adder, with the result in the display board. It blocks the conversion of binary to BCD and multiplexed displays.
Date
: 2025-07-22
Size
: 396kb
User
:
Paulo
chuankou
Downloaded:0
VHDL-based serial communication, including schematic and VHDL input
Date
: 2025-07-22
Size
: 256kb
User
:
小陈
tiaozhijietiaoqi
Downloaded:0
This example is designed modem VHDL code, and changed completely the use of text input module
Date
: 2025-07-22
Size
: 834kb
User
:
小陈
signalgenerator
Downloaded:0
Written using the VHDL function signal generator, the module uses text input
Date
: 2025-07-22
Size
: 359kb
User
:
小陈
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