VHDL-FPGA-Verilog List Page 3269

VHDL-FPGA-Verilog list

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keyboard Downloaded：0: verilog to achieve keyboard-driven features, basic letter keys input, case conversion functions, interact with the host computer through the serial port
Date : 2025-07-21 Size : 1kb User : 柳林
shudian Downloaded：0: Digital clock-related procedures, to achieve the automatic beating of time, but also changes in time, the whole point timekeeping
Date : 2025-07-21 Size : 403kb User : meng
CPU16 Downloaded：0: Own use VHDL to write a 16-bit CPU, in school curriculum passed the test.
Date : 2025-07-21 Size : 1.13mb User : Hui
DM642_network_video_source Downloaded：0: DM642_network_video_source our graduate program to use, it is common
Date : 2025-07-21 Size : 1.46mb User : 军军
IIR Downloaded：0: Experiment description: this experiment to achieve an IIR filter, and the ISE inside the simulation. \ rtl directory which is the source file \ project directory which is the project
Date : 2025-07-21 Size : 2.58mb User : 军军
seg Downloaded：0: Procedure Description: This development board above the experimental control of digital control. \ 1-f folder inside the tube from a digital program control is beginning to show, and gradually add 1 until f. \ 1234 folde
Date : 2025-07-21 Size : 427kb User : 军军
uart Downloaded：0: Procedure Note: The experimental control development board above the serial port to communicate with the PC machine, and the serial wizard inside the display characters. Catalog Description: The project \ project folder
Date : 2025-07-21 Size : 884kb User : 军军
usb Downloaded：0: Procedure Note: In this experiment, control development board USB, and PC, to communicate, and display character. Catalog Description: The project \ project folder inside the source file and pins distributed in \ rtl fol
Date : 2025-07-21 Size : 79kb User : 军军
sdram Downloaded：0: Procedure Note: In this experiment, control development board to complete the above SDRAM read and write capabilities. SDRAM write data inside first and then read out the data to compare, if you do not match on the adopt
Date : 2025-07-21 Size : 761kb User : 军军
song Downloaded：0: module song (clk, key, song_out, led) input [7:0] key input clk output song_out output [7:0] led reg song_reg reg [21:0] count reg [19:0 ] delay reg [7:0] key_reg always @ (posedge clk) begin count = count+1 if ((count =
Date : 2025-07-21 Size : 357kb User : 罗仲景
123 Downloaded：0: Another FPGA internal digital-analog conversion is easy to achieve increased resolution, the use of
Date : 2025-07-21 Size : 5kb User : 王毅
counter Downloaded：0: 4 synchronous loadable counter, an asynchronous set, controlled by the control key down, or down the count. Count the state from the seven digital tube display.
Date : 2025-07-21 Size : 238kb User : 心晨

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