VHDL-FPGA-Verilog List Page 3011

VHDL-FPGA-Verilog list

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hw_for_sw Downloaded：0: vhdl. verilog,实用例程,希望对大家有帮助
Date : 2025-11-17 Size : 1.12mb User : 夏盛
Spartan3E_ADC Downloaded：0: Xilinx the spartan3e specific development board ADC conversion program, absolutely free, simulation by
Date : 2025-11-17 Size : 3kb User : 雍振强
cof Downloaded：0: cafe
Date : 2025-11-17 Size : 1kb User : sara
Solutions Downloaded：0: `timescale 1ns / 1ps module AND_OR(INP, OUT1) input [3:0] INP output OUT1 wire SIG1, SIG2 MY_AND2 U0 (.A(INP[0]), .B(INP[1]), .C(SIG1)) MY_AND2 U1 (.A(INP[2]), .B(INP[3]), .C(SIG2)) MY_OR2 U2 (.A(SIG1), .B(SIG2), .C(OUT1
Date : 2025-11-17 Size : 7kb User : qweabc
EDA Downloaded：0: Add 8-bit hardware multiplier shift circuit design, the multiplier is composed of 8-bit adder to temporal order, 8-bit multiplier design.
Date : 2025-11-17 Size : 34kb User : zhangyue
EDA2 Downloaded：0: NC crossover study design, analysis and testing methods. NC divider function is that when the input given different input data, input the clock signal will have a different frequency than, NC divider is in parallel with
Date : 2025-11-17 Size : 44kb User : zhangyue
EDA4 Downloaded：0: 1, familiar with the Quartus software use and design flow. 2, using macro control module design method, which uses port and parameter definition of the macro function module generation. 3, grasp the sinusoidal signal gen
Date : 2025-11-17 Size : 621kb User : zhangyue
VHDL1 Downloaded：0: Learning to use FPGA to design a signal generator, the choice of output to the input signal increases, decreasing sawtooth, triangle, ladder wave and square wave.
Date : 2025-11-17 Size : 390kb User : zhangyue
BX Downloaded：0: Sine signal, triangle wave, sawtooth waveforms of three the same time requirements for sinusoidal waveforms to produce step
Date : 2025-11-17 Size : 969kb User : zdan
dds Downloaded：0: dds
Date : 2025-11-17 Size : 2kb User : kelas
IFFT-RTL Downloaded：0: the verilog code for IFFT algorithm
Date : 2025-11-17 Size : 273kb User : 李慧
123 Downloaded：0: Verilog是广泛应用的硬件描述语言，可以用在硬件设计流程的建模、综合和模拟等多个阶段。随着硬件设计规模的不断扩大，应用硬件描述语言进行描述的CPLD结构，成为设计专用集成电路和其他集成电路的主流。通过应用Verilog HDL对多功能电子钟的设计，达到对Verilog HDL的理解，同时对CPLD器件进行简要了解。
Date : 2025-11-17 Size : 587kb User : 和

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