VHDL-FPGA-Verilog List Page 3014

VHDL-FPGA-Verilog list

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counter Downloaded：0: FPGA VHDL COUNTER
Date : 2025-11-17 Size : 111kb User : CG
reference Downloaded：0: These are our IC design curriculum outcome, written with Verilog language. It is mainly about the interleave and deinterleave which is based on the IEEE802.3 Protocal. In the deinterleave, there may be some wrong time sh
Date : 2025-11-17 Size : 652kb User : gy
de2sound Downloaded：0: This design combines audio input from the microphone and line in signals and outputs the result to the line out signal. Connect a microphone to the MIC port, an audio source to the LINE IN port, and speakers/headphones t
Date : 2025-11-17 Size : 103kb User : 胡伟
AtmelFPGAPwm Downloaded：0: atmel fpga pwm implimentation docs
Date : 2025-11-17 Size : 144kb User : rebiha
AD7864 Downloaded：0: AD7864 control logic. Verilog language.
Date : 2025-11-17 Size : 14kb User : zhangwei
logic Downloaded：0: AD control logic multi-channel scanning
Date : 2025-11-17 Size : 125kb User : zhangwei
ADset Downloaded：0: AD9222 to receive instruction logic. (Verilog language)
Date : 2025-11-17 Size : 1kb User : zhangwei
DDS_Set Downloaded：0: AD9852, DDS chips receive data logic. (Verilog language)
Date : 2025-11-17 Size : 1kb User : zhangwei
coef_reload91 Downloaded：0: Altera filter coefficients can be overloaded code, from its official website
Date : 2025-11-17 Size : 94kb User : ooakk
shuzizhong Downloaded：0: To achieve a simple digital clock signal, by 11 parts, the top-level file is a digital clock.
Date : 2025-11-17 Size : 1.75mb User : gdfrg
fifo89 Downloaded：0: FIFO FIFO buffer, 8-bit word wide, 9-bit words deep, very simple buffers.
Date : 2025-11-17 Size : 263kb User : gdfrg
altera_fft Downloaded：0: Alter' s FFT of the IP core source code, software running in QuartusII
Date : 2025-11-17 Size : 967kb User : 吴琼

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