VHDL-FPGA-Verilog List Page 3017

VHDL-FPGA-Verilog list

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ad8113 Downloaded：0: fpga have ad conversion, digital-analog conversion capabilities to complete good effect, output stability
Date : 2025-11-17 Size : 15.09mb User : Jacky.king
yejing1602 Downloaded：0: fpga finished LCD module test functions, good effect, first clear
Date : 2025-11-17 Size : 1.01mb User : Jacky.king
jtd Downloaded：0: TRIFFIC LIGHT VHDL
Date : 2025-11-17 Size : 1kb User : 李楠
ditong Downloaded：0: Ewb design low-pass filter, low pass filter ewb design
Date : 2025-11-17 Size : 66kb User : wujian
VHDL_code_for_DAC_controller Downloaded：0: An VHDL code designs are presented ,it is for controlling the AD7524 digital-to-analogue converter
Date : 2025-11-17 Size : 1kb User : jimmy sia
Thyristor_gate_control_pulse_generator Downloaded：0: An example VHDL code designs are presented,it is for controlling an example thyristor.
Date : 2025-11-17 Size : 1kb User : jimmy sia
wcy Downloaded：0: FPGA-based direct digital synthesizer (DDS) design (source code)
Date : 2025-11-17 Size : 655kb User : wangchuanyang
exer1 Downloaded：0: verilog big job title, description of a remote control with Verilog simulation and synthesis of the circuit
Date : 2025-11-17 Size : 54kb User : 林涛
exer2 Downloaded：0: Given a frequency of 33MHz clock, try to use the clock to get a basic uniform of the 2.048MHz clock
Date : 2025-11-17 Size : 27kb User : 林涛
exer3 Downloaded：0: 3, the circuit using as little as possible, find two positive integers less than the 100 greatest common divisor and least common multiple. (Not allowed to use mod function), and integrated a circuit simulation
Date : 2025-11-17 Size : 58kb User : 林涛
exer4 Downloaded：0: Design of the two athletes running the stopwatch timing, verilog great job
Date : 2025-11-17 Size : 59kb User : 林涛
project4 Downloaded：0: A 14-stage FIR filter design, has given the filter coefficients and the validation process
Date : 2025-11-17 Size : 9kb User : 林涛

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