`timescale 1ns / 1ps module AND_OR(INP, OUT1) input [3:0] INP output OUT1 wire SIG1, SIG2 MY_AND2 U0 (.A(INP[0]), .B(INP[1]), .C(SIG1)) MY_AND2 U1 (.A(INP[2]), .B(INP[3]), .C(SIG2)) MY_OR2 U2 (.A(SIG1), .B(SIG2), .C(OUT1)) endmodule

Solutions\ADDR_CNTR.v
.........\AND_OR.v
.........\AND_OR_TB.v
.........\CLK_DIV.v
.........\LED_DRIVER.ucf
.........\LED_DRIVER.v
.........\MEM.v
.........\MY_AND2.v
.........\MY_CNTR.v
.........\MY_CNTR_TB.v
.........\MY_HEADER.txt
.........\MY_INPUT.txt
.........\MY_OR2.v
.........\SECURITY_1.v
.........\SECURITY_1_TB.v
.........\SP_RAM8x16.v
.........\SP_RAM8x16_TB.v
.........\SP_RAM8x16_TB_solution.v
Solutions

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