VHDL-FPGA-Verilog List Page 3008

VHDL-FPGA-Verilog list

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Verilog Downloaded：0: Verilog language exercises and explain the Chinese version. Pdf
Date : 2025-11-18 Size : 3.23mb User : 尤路
DDS_100325(13)_success Downloaded：0: QUARTUS II environment, VHDL language DDS program, two digital signal output, an amplitude for the sine wave output, a sine wave difference signal. Clock 2 ^ 21HZ, with 24bits frequency control word.
Date : 2025-11-18 Size : 1.04mb User : 骆东君
190.7_Freq_divider Downloaded：0: QUARTUS II, prepared under the decimal divider VHDL program to achieve 190.7 frequency, you can divide into a 50MHz clock frequency is about equal to 2 ^ 21Hz frequency, easy operation under special circumstances
Date : 2025-11-18 Size : 320kb User : 骆东君
rs232 Downloaded：0: FPGA Digital Filter Algorithm for information, they can design LMS algorithm
Date : 2025-11-18 Size : 58kb User : suupy
iiscode Downloaded：0: Develop an iis controller with verilog hdl. The key parts of iis were departed in two. One is clkgen.v which generate the clk and sync singnal we want and the transcon.v is used for contrl the FSM of the iis.
Date : 2025-11-18 Size : 591kb User : hgdai
deng Downloaded：0: deng Colourful light electric circuit, Quartus7.2, act cloth type, ambulation type
Date : 2025-11-18 Size : 54kb User : 柠檬
SOPC Downloaded：0: Can display hours, minutes, seconds, 24-hour system can set a time at night is not the newspaper
Date : 2025-11-18 Size : 1.53mb User : 张锐
I2C-BusDesign Downloaded：0: This procedure gives the complete design of the project file and I2C VHDL source code
Date : 2025-11-18 Size : 76kb User : RoyHunter
VGA-VHDL-Design Downloaded：0: This document is presented based on VHDL language VGA image display program and the project asked the pieces.
Date : 2025-11-18 Size : 39kb User : RoyHunter
serial-VHDL-Deign Downloaded：0: This procedure is to verify the function module and the PC machine to achieve a basic serial communication functions. Need to install a serial PC, debugging tools to verify functionality of the program.
Date : 2025-11-18 Size : 64kb User : RoyHunter
LCD-VHDL-Design Downloaded：0: This procedure is to verify the function module to achieve LCD liquid crystal display.
Date : 2025-11-18 Size : 485kb User : RoyHunter
AD_TLC549_TEST Downloaded：0: The program module within the AD converter in the FPGA module. Analog AD_TLC549 converter.
Date : 2025-11-18 Size : 201kb User : RoyHunter

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