VHDL-FPGA-Verilog List Page 3004

VHDL-FPGA-Verilog list

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trafficlight Downloaded：0: Simple two-way traffic lights can be set to the number of seconds
Date : 2025-11-18 Size : 1kb User : 魏鉉諳
DDS__VERILOG____ Downloaded：0: Achieve dds, dds design can be achieved, is my collection
Date : 2025-11-18 Size : 3kb User : energy
jipinqicepinzhou Downloaded：0: Frequency meter, there are two measuring methods, that is, the frequency measurement and test week, we put forward to use frequency measure, but sometimes the teacher will let us write the choice of frequency measurement
Date : 2025-11-18 Size : 629kb User : amy
daling Downloaded：0: MUXPLUSII platform using industry fight bell function.
Date : 2025-11-18 Size : 748kb User : amy
Verilogexamples Downloaded：0: Verilog beginner programming examples, including source code and Quartus Ⅱ simulation results, suitable for beginners to understand the learning
Date : 2025-11-18 Size : 3.47mb User : kinderce
VHDL_clock Downloaded：0: VHDL design process digital clock design basic requirements: 1.24 hours count display 2, when a school function (hour, minute) additional requirements: 1, to achieve alarm (time, alarm sound) -
Date : 2025-11-18 Size : 70kb User : 苹果熊
traffic Downloaded：0: traffic lights
Date : 2025-11-18 Size : 187kb User : zz
A_VHDL_process_elevator_controller Downloaded：0: An elevator controller VHDL procedures: A VHDL process elevator controller
Date : 2025-11-18 Size : 117kb User : jk
jiyufpgazhijiepinlvhechengqi Downloaded：0: Direct frequency synthesizer FPGA design, novel and unique, good reference frequency synthesizer, in particular the use of logic gate arrays have reference value.
Date : 2025-11-18 Size : 146kb User : 烟雨楼
ans Downloaded：0: Digital Competition Responder features a realization. Quad Responder function, with time out and answer time-out function Responder 2. Scoring display, each corresponding to the two digital control, can display the score
Date : 2025-11-18 Size : 411kb User : lhr
byteblaster Downloaded：0: Altera a detailed description of the parallel port download cable data, with it, you can create a download cable own it!
Date : 2025-11-18 Size : 100kb User : 王家祥
altera_de2_vhdl Downloaded：0: Tutorial of VHDL with Altera DE2 board: quartus II and DE2 board The target do the BCD sum of input data coded with the switches and display the result on 7 segment display
Date : 2025-11-18 Size : 576kb User : candido

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