This procedure is to verify the function module and the PC machine to achieve a basic serial communication functions. Need to install a serial PC, debugging tools to verify functionality of the program.

serial-VHDL-Deign\Block1.bdf
.................\serial.asm.rpt
.................\serial.bdf
.................\serial.bsf
.................\serial.cdf
.................\serial.done
.................\serial.fit.eqn
.................\serial.fit.rpt
.................\serial.fit.smsg
.................\serial.fit.summary
.................\serial.flow.rpt
.................\serial.map.eqn
.................\serial.map.rpt
.................\serial.map.summary
.................\serial.pin
.................\serial.pof
.................\serial.qpf
.................\serial.qsf
.................\serial.qws
.................\serial.sof
.................\serial.tan.rpt
.................\serial.tan.summary
.................\serial_assignment_defaults.qdf
.................\serial_test.bsf
.................\serial_test.vhd
.................\serial_test.vhd.bak
.................\setup.tcl
.................\setup.tcl.bak
serial-VHDL-Deign

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