VHDL-FPGA-Verilog List Page 2944

VHDL-FPGA-Verilog list

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led_test Downloaded：0: led vhdl test programe in Quartus II
Date : 2025-11-19 Size : 167kb User : 程光
measure Downloaded：0: Pulse width measurement circuit, active low, the maximum pulse width measurement 256 film, if overflow beyond the reported
Date : 2025-11-19 Size : 318kb User : 梅松
cnt_test Downloaded：0: Counter programe used in VHDL,devlopment tool:Quartus ii 6.0
Date : 2025-11-19 Size : 156kb User : 程光
pipeline Downloaded：0: With a line consisting of eight serial adder, can output binary cascade
Date : 2025-11-19 Size : 508kb User : 梅松
B_to_D Downloaded：0: BCD binary code change process, as 7 digital display codec process, VHDL FPGA project prepared.
Date : 2025-11-19 Size : 986kb User : 程光
uart_verilog Downloaded：0: UART programming procedures after using the verilog want to help debugging
Date : 2025-11-19 Size : 7kb User : gaoyueshan
FPGA Downloaded：0: FPGA time delay and timer control
Date : 2025-11-19 Size : 425kb User : hongshan
Verilog000 Downloaded：0: Verilog语言的学习，熟悉Verilog语言的各种语法。 ②、FPGA的学习，熟悉QuartusII软件的各种功能，各种逻辑算法设计，接口模块(RS232,LCD,VGA,SPI,I2c等)的设计，时序分析，硬件优化等，自己开始设计简单的FPGA板子。 ③、NiosII的学习，熟悉NiosII的开发流程，熟悉开发软件(SOPC,NiosII IDE),了解NiosII的基本结构，设计NiosII开发板，编写NiosII C语言程序，
Date : 2025-11-19 Size : 21.74mb User : onejacky
vhdl_design_of_finite_state_machine Downloaded：0: the design of finite state machine vhdl vhdl design of finite state machine
Date : 2025-11-19 Size : 106kb User : 张c
VHDL_FPGA_design_technology Downloaded：0: VHDL, FPGA design technology VHDL, FPGA design technology, answers to frequently asked questions marriage without good documentation
Date : 2025-11-19 Size : 143kb User : 张c
Courseware_for_teaching_classical_VHDL Downloaded：0: VHDL teaching classical Courseware Courseware for teaching classical VHDL
Date : 2025-11-19 Size : 107kb User : 张c
VHDL_house_training_materials Downloaded：0: VHDL-house training materials VHDL-house training materials, a good reference material and learning
Date : 2025-11-19 Size : 269kb User : 张c

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