VHDL-FPGA-Verilog List Page 2942

VHDL-FPGA-Verilog list

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fpga_frequency_circuit_design Downloaded：0: fpga frequency circuit design fpga frequency circuit design explained in detail the classification of sub-frequency circuit
Date : 2025-11-19 Size : 143kb User : xiaoli
Classic_application_of_EDA_technologies Downloaded：0: Classic application of EDA technology is good, oh the vhdl routines, eda an important part of
Date : 2025-11-19 Size : 295kb User : xiaoli
spartan2e_and_spartan3_xc2s300e-6pq208 Downloaded：0: spartan2e and spartan3 and spartan2e series chip xc2s300e-6pq208 data (datasheet)
Date : 2025-11-19 Size : 3.09mb User : 关明明
lab_manual_tutorial Downloaded：0: 4- Bit Counter with Xilinx ISE 9.2 and Spartan 3E
Date : 2025-11-19 Size : 312kb User : 飞飞三号
Lab01 Downloaded：0: To become familiar with using Xilinx ISE to draw schematic representations of PLD circuits To become familiar with using Xilinx ISE to conduct graphical waveform simulations of PLD circuits To become familiar with using
Date : 2025-11-19 Size : 1.19mb User : 飞飞三号
Tutorial_5 Downloaded：0: The sequence detector will look for the input series “10010.” LED’s will show how much of the series has been detected and when the entire series has been entered an additional LED will come on. Circuit input will be con
Date : 2025-11-19 Size : 1.17mb User : 飞飞三号
Tutorial09_Clock Downloaded：0: A very important concept in digital design is that of the clock. A clock is used to synchronize systems in digital logic, and provides a convenient way to keep track of real time. Another equally important fact is the ab
Date : 2025-11-19 Size : 405kb User : 飞飞三号
mix Downloaded：0: This code is based on the Verilog language, is the Galois field GF (2 ^ 8) on the completion of addition and multiplication, the main column of the completion of ASE encryption hybrid operation
Date : 2025-11-19 Size : 225kb User : 钟佳荣
20100728 Downloaded：0: Reading a good clear design concept and method registers, registers on the FPGA design has good design inspiration
Date : 2025-11-19 Size : 75kb User : lifei
shift_reg Downloaded：0: actel fpga ap030 regshift
Date : 2025-11-19 Size : 291kb User : liu
duc_ddc_system_generator Downloaded：0: This paper introduces the process of using the system generator to design digital frequency conversion DDC in the xilinx environment, which is very helpful for beginners
Date : 2025-11-19 Size : 2.41mb User : 谢宾
VHDLshiyingjiaocheng Downloaded：0: VHDL practical course, a very detailed example, novice to learn essential
Date : 2025-11-19 Size : 54.7mb User : xiaosolider

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