VHDL-FPGA-Verilog List Page 2948

VHDL-FPGA-Verilog list

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Synopsys_Graphical_Environment_User_Guide Downloaded：0: Synopsis software GUI operation guide for the FPGA/ASIC is useful for beginners!
Date : 2025-11-19 Size : 1mb User : HY
digitaldesignwithPLD Downloaded：0: Programmable Logic
Date : 2025-11-19 Size : 10.49mb User : wangran
MAX263-MAX268 Downloaded：0: MAX263，MAX264，MAX265，MAX266，MAX267，MAX268
Date : 2025-11-19 Size : 3.93mb User : 雪域高原
fallthrough_small_fifo_v2 Downloaded：0: Synchronous fifo design, simulation has been adopted, written with Verilog, code short
Date : 2025-11-19 Size : 1kb User : xinghuo
small_fifo Downloaded：0: Synchronous fifo design, simulation has been adopted, written with Verilog, code short and easy to understand
Date : 2025-11-19 Size : 1kb User : xinghuo
verilog Downloaded：0: Differences between different Verilog language and Verilog language version of the characteristics of high
Date : 2025-11-19 Size : 3kb User : xinghuo
modelsim6.0 Downloaded：0: modelsim Chinese user manual, and they hope people who want to learn a useful mldelsim
Date : 2025-11-19 Size : 379kb User : xinghuo
256fft Downloaded：0: • 256 -point radix-8 FFT. • Forward and inverse FFT. • Pipelined mode operation, each result is outputted in one clock cycle, the latent delay from input to output is equal to 580 clock cycles (839 clock c
Date : 2025-11-19 Size : 205kb User : Nagendran
matrix Downloaded：0: 3x3 matrix implementation in VHDL
Date : 2025-11-19 Size : 724kb User : Nagendran
cFFT Downloaded：0: CFFT is a radix-4 fast Fourier transform (FFT) core with configurable data width and a configurable number of sample points in the FFT. Twiddle factors are implemented using the CORDIC algorithm, causing the gain of the
Date : 2025-11-19 Size : 179kb User : Nagendran
viterbi Downloaded：0: This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog
Date : 2025-11-19 Size : 639kb User : Nagendran
lowpowerfir Downloaded：0: This project was undertaken to produce a low power FIR filter for inclusion in a VHDL target library. The design was completed using OrCAD s Capture CIS, from this the VHDL code has been extracted. This method has allowe
Date : 2025-11-19 Size : 437kb User : Nagendran

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