VHDL-FPGA-Verilog List Page 2735

VHDL-FPGA-Verilog list

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2BCD Downloaded：0: Binary to BCD code verilog hdl Quartus II 9.0sp2 compile all the documents
Date : 2025-11-21 Size : 280kb User : 王冠
ftdd Downloaded：0: Implemented in fpga function demosaicing
Date : 2025-11-21 Size : 2kb User : 吴佳良
UART Downloaded：0: A sample that describe how to make wiring between modules using verilog ,it contain two stages of inverter of SW1 as input and LD7 as output
Date : 2025-11-21 Size : 748kb User : xzorox
MSP430C Downloaded：0: JPEG with the FPGA implementation of the Verilog source code
Date : 2025-11-21 Size : 733kb User : 杜晓伟
exp_cpu_vhd Downloaded：0: A CPU module except downloading parts,such as SHIXU and XIANSHI.This version has 2 warning as below.But functional waveform shows --a right execution of computing. --ZHANG Hongjie 2010.6.11 -- Warning: Inferred dual-cloc
Date : 2025-11-21 Size : 2kb User : doufangzheng
screw Downloaded：0: A nice scrambler, mainly used in optical fiber communication above. Because in order to maintain the optical module of the signal is not sent to all 1 or all 0
Date : 2025-11-21 Size : 1kb User : 刘金华
verilog_16_SRAM Downloaded：0: Verilog test sram
Date : 2025-11-21 Size : 699kb User : 王亮
verliog_VGA Downloaded：0: verilog to vga
Date : 2025-11-21 Size : 377kb User : 王亮
verilog_DA_TLC5615 Downloaded：0: verilog 1K~10KHz test
Date : 2025-11-21 Size : 687kb User : 王亮
EDACLOCK Downloaded：0: EDA design of a digital clock on the report, to share, we want to help
Date : 2025-11-21 Size : 82kb User : zhao wei
jiaocheng Downloaded：0: This document describes a variety of digital system design principle of the experiment and its source code, etc.
Date : 2025-11-21 Size : 2.52mb User : 张鹏
FIR_matlab_verilog Downloaded：0: using matlab to simulate a fir lowpass, then using verilog to implement it.
Date : 2025-11-21 Size : 3kb User : Fengxiaodong

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