VHDL-FPGA-Verilog List Page 2732

VHDL-FPGA-Verilog list

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Altera_FPGA_CPLD_Designing(Advanced) Downloaded：0: Altera_FPGA_CPLD_Designing(Advanced)
Date : 2025-11-21 Size : 20.39mb User : 彭军
uart_rar_testbench Downloaded：0: code VHDL uart mode code VHDL uart mode
Date : 2025-11-21 Size : 3kb User : o0o0o0o0o0
uart2bus_latest.tar Downloaded：0: Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
Date : 2025-11-21 Size : 219kb User : robin
vhdluartmode Downloaded：0: code VHDL uart mode code VHDL uart mode
Date : 2025-11-21 Size : 1kb User : o0o0o0o0o0
GXIV_SIBoard_1Ch_Multi_Prbs_155Mbps_Clock_Recovery Downloaded：0: Altera provided on the official website over the routine sampling and data recovery is very rare.
Date : 2025-11-21 Size : 4.82mb User : robin
an490 Downloaded：0: Official website of the MAXII Altera CPLD family to do the application-level document conversion, very practical.
Date : 2025-11-21 Size : 375kb User : robin
fft_256 Downloaded：0: failed to translate
Date : 2025-11-21 Size : 24kb User : Cxgu
FPGA_VHDL_exambles Downloaded：0: 27 FPGA VHDL examples, including source code and simulation procedure is a good material for beginners.
Date : 2025-11-21 Size : 1.22mb User : huangguilin
AES Downloaded：0: AES implementation in VHDL@!
Date : 2025-11-21 Size : 509kb User : manishrb
fifo Downloaded：0: frist in frist out in pdf format
Date : 2025-11-21 Size : 77kb User : Mr.
carLights-prelab Downloaded：0: vhdl sample of car lights which is a good example code for beginners for vhdl
Date : 2025-11-21 Size : 1kb User : jshin
carLightsMealy Downloaded：0: carlights example with mealy based vhdl good for study
Date : 2025-11-21 Size : 1kb User : jshin

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