verilog to vga

进阶实验_06_VGA ：直接输出到CRT，场频60，行频36\Quartus\db\prev_cmp_VGA_CTL.asm.qmsg
........................................................\.......\..\prev_cmp_VGA_CTL.fit.qmsg
........................................................\.......\..\prev_cmp_VGA_CTL.map.qmsg
........................................................\.......\..\prev_cmp_VGA_CTL.qmsg
........................................................\.......\..\prev_cmp_VGA_CTL.tan.qmsg
........................................................\.......\..\VGA_CTL.asm.qmsg
........................................................\.......\..\VGA_CTL.asm_labs.ddb
........................................................\.......\..\VGA_CTL.cbx.xml
........................................................\.......\..\VGA_CTL.cmp.bpm
........................................................\.......\..\VGA_CTL.cmp.cdb
........................................................\.......\..\VGA_CTL.cmp.ecobp
........................................................\.......\..\VGA_CTL.cmp.hdb
........................................................\.......\..\VGA_CTL.cmp.kpt
........................................................\.......\..\VGA_CTL.cmp.logdb
........................................................\.......\..\VGA_CTL.cmp.rdb
........................................................\.......\..\VGA_CTL.cmp.tdb
........................................................\.......\..\VGA_CTL.cmp0.ddb
........................................................\.......\..\VGA_CTL.cmp2.ddb
........................................................\.......\..\VGA_CTL.cmp_merge.kpt
........................................................\.......\..\VGA_CTL.db_info
........................................................\.......\..\VGA_CTL.eco.cdb
........................................................\.......\..\VGA_CTL.fit.qmsg
........................................................\.......\..\VGA_CTL.hier_info
........................................................\.......\..\VGA_CTL.hif
........................................................\.......\..\VGA_CTL.lpc.html
........................................................\.......\..\VGA_CTL.lpc.rdb
........................................................\.......\..\VGA_CTL.lpc.txt
........................................................\.......\..\VGA_CTL.map.bpm
........................................................\.......\..\VGA_CTL.map.cdb
........................................................\.......\..\VGA_CTL.map.ecobp
........................................................\.......\..\VGA_CTL.map.hdb
........................................................\.......\..\VGA_CTL.map.kpt
........................................................\.......\..\VGA_CTL.map.logdb
........................................................\.......\..\VGA_CTL.map.qmsg
........................................................\.......\..\VGA_CTL.map_bb.cdb
........................................................\.......\..\VGA_CTL.map_bb.hdb
........................................................\.......\..\VGA_CTL.map_bb.logdb
........................................................\.......\..\VGA_CTL.pre_map.cdb
........................................................\.......\..\VGA_CTL.pre_map.hdb
........................................................\.......\..\VGA_CTL.rtlv.hdb
........................................................\.......\..\VGA_CTL.rtlv_sg.cdb
........................................................\.......\..\VGA_CTL.rtlv_sg_swap.cdb
........................................................\.......\..\VGA_CTL.sgdiff.cdb
........................................................\.......\..\VGA_CTL.sgdiff.hdb
........................................................\.......\..\VGA_CTL.sld_design_entry.sci
........................................................\.......\..\VGA_CTL.sld_design_entry_dsc.sci
........................................................\.......\..\VGA_CTL.syn_hier_info
....

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