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VHDL-FPGA-Verilog list
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FinalTLC
Downloaded:0
Traffic Light Controller
Date
: 2025-11-21
Size
: 1.21mb
User
:
Charles
1
Downloaded:0
Channel 0 capture by ADC0809 potentiometer value and processed through the DAC0832 output, the output directly connected to the ADC0809' s Channel 1, and IN1 IN0, and the data collected were displayed on the LED, and
Date
: 2025-11-21
Size
: 3kb
User
:
dflipflop
Downloaded:0
d flipflop for verilog code
Date
: 2025-11-21
Size
: 2kb
User
:
mella
add8
Downloaded:0
carry look ahead 8 bit adder
Date
: 2025-11-21
Size
: 5kb
User
:
pradeep
VGA_TEST
Downloaded:0
Implemented using verilog HDL VGA interface, debugging success, can be used directly
Date
: 2025-11-21
Size
: 1kb
User
:
向平
shuzishizhong
Downloaded:0
VHDL implementation of serial communication with the source code to adjust pass, can be used directly!
Date
: 2025-11-21
Size
: 318kb
User
:
向平
DC
Downloaded:0
Design Compiler have the information, very detailed, up some for a comprehensive ASIC Design Compiler for helpful
Date
: 2025-11-21
Size
: 12.15mb
User
:
iyoung
xie
Downloaded:0
write operation to hard disk sector through the IDE interface , DMA mode of the source code
Date
: 2025-11-21
Size
: 58kb
User
:
wang
du
Downloaded:0
write operation to hard disk sector through the IDE interface , DMA mode of the source code
Date
: 2025-11-21
Size
: 58kb
User
:
wang
qiduanshumaguandongtaixianshi0000-9999
Downloaded:0
Seven-Segment LED dynamic display design using vhdl language compiler has passed
Date
: 2025-11-21
Size
: 416kb
User
:
王冠
01chufaqi
Downloaded:0
0 with synchronous clear, synchronous set 1 D flip-flop verilog language description
Date
: 2025-11-21
Size
: 224kb
User
:
王冠
miaobiao
Downloaded:0
Digital display with stopwatch verilog language Quartus II 9.0sp2 successfully compiled all the files have been generated that contains
Date
: 2025-11-21
Size
: 498kb
User
:
王冠
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.34
.35
.36
.37
.38
2739
.40
.41
.42
.43
.44
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4310
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