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VHDL-FPGA-Verilog list
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8-ADDER-VHDL
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Using hardware description language preparation 8 bits QuanJia implement code, very useful!!
Date : 2025-11-22 Size : 1kb User : 王浩彬
HALF-ADDER-VHDL
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Using hardware description language preparation 8 bits QuanJia implement code, is very practical through the code compiler and waveform test shows the design is fully meet the requirements, and design of the circuit diag
Date : 2025-11-22 Size : 1kb User : 王浩彬
CLA4
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Carry look Ahead Adder using top level
Date : 2025-11-22 Size : 52kb User : Yanal
gam1
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A Low-power Variable-length FFT Processor Base on Radix-24 Algorithm
Date : 2025-11-22 Size : 1.18mb User : rams
gam2
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A Low-power Variable-length FFT Processor Base on Radix-24 Algorithm
Date : 2025-11-22 Size : 968kb User : rams
gam3
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FPGA Implementation ofLow Power 64-Point Radix-4 FFT Processor for OFDM System
Date : 2025-11-22 Size : 142kb User : rams
gam5
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FPGA Implementation ofLow Power 64-Point Radix-4 FFT Processor for OFDM System
Date : 2025-11-22 Size : 1.22mb User : rams
gam7
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FPGA Implementation ofLow Power 64-Point Radix-4 FFT Processor for OFDM System
Date : 2025-11-22 Size : 14.83mb User : rams
12
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cordic algorithm using verilog code
Date : 2025-11-22 Size : 1kb User : rams
freefifo
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a test program of sys fifo
Date : 2025-11-22 Size : 5kb User : 庄敏敏
4QAM-NR
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This is based on the 2008 GB DMB_TH in 4QAM_NR mapped FPGA, including the mapping table
Date : 2025-11-22 Size : 574kb User : 庄敏敏
ASI_IN1_and_ASI_OUT1
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This received from the satellite down for the TS stream, there are two streams of their choice, including the synchronization module, PCR correction module, rate adjustment module
Date : 2025-11-22 Size : 2.31mb User : 庄敏敏
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