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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2012-11-26
  • Size : 52kb
  • Downloaded :0次
  • Author :Ya***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Carry look Ahead Adder using top level
Packet file list
(Preview for download)
CLA4
....\.lso
....\CLA16.cmd_log
....\CLA16.lso
....\CLA16.ngc
....\CLA16.ngr
....\CLA16.prj
....\CLA16.stx
....\CLA16.syr
....\CLA16.v
....\CLA16.xst
....\CLA16_xst.xrpt
....\CLA4.cmd_log
....\CLA4.gise
....\CLA4.lso
....\CLA4.ngc
....\CLA4.ngr
....\CLA4.prj
....\CLA4.stx
....\CLA4.syr
....\CLA4.v
....\CLA4.xise
....\CLA4.xst
....\CLA4_envsettings.html
....\CLA4_summary.html
....\CLA4_xst.xrpt
....\ipcore_dir
....\iseconfig
....\.........\CLA4.projectmgr
....\.........\CLA4.xreport
....\webtalk_pn.xml
....\xst
....\...\dump.xst
....\...\........\CLA16.prj
....\...\........\.........\ngx
....\...\........\.........\...\notopt
....\...\........\.........\...\opt
....\...\........\CLA4.prj
....\...\........\........\ngx
....\...\........\........\...\notopt
....\...\........\........\...\opt
....\...\projnav.tmp
....\...\work
....\...\....\hdllib.ref
....\...\....\vlg1C
....\...\....\.....\_c_l_a4.bin
....\...\....\vlg33
....\...\....\.....\_c_l_a16.bin
....\_xmsgs
....\......\pn_parser.xmsgs
....\......\xst.xmsgs
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