VHDL-FPGA-Verilog List Page 2601

VHDL-FPGA-Verilog list

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cotas Downloaded：0: Costas loop is used to double sideband suppressed carrier signal demodulation, and also two-phase or four phase shift keying signal demodulation of the special loop
Date : 2025-11-22 Size : 3kb User : 陈华
crc_16 Downloaded：0: 16-bit CRC (cyclic redundancy check code), CRC is the data communications of the most commonly used error checking code, which is characterized by the information field and check the length of the field can be arbitraril
Date : 2025-11-22 Size : 1kb User : 陈华
adder16_2 Downloaded：0: Two 16-bit binary numbers together, were added to high and high, low and low sum.
Date : 2025-11-22 Size : 1kb User : 陈华
cordic Downloaded：0: CORDIC (Coordinate Rotation Digital Computer) algorithm for the coordinate rotation digital calculation. CORDIC algorithm can be achieved through the rapid translation and accumulation based on mathematical functions, in
Date : 2025-11-22 Size : 1kb User : 陈华
QPSK Downloaded：1: Verilog language using QPSK modulation, QPSK is a digital modulation. It is divided into absolute and relative phase shift of the phase shift of two.
Date : 2025-11-22 Size : 1kb User : 陈华
linearcode Downloaded：0: linearcode linear encoder: for wireless communication linear encoders
Date : 2025-11-22 Size : 1kb User : 陈华
winphlash1716 Downloaded：0: WinPhlash rare program for reflash Phoenix bios
Date : 2025-11-22 Size : 959kb User : rtfyrft
PIDctrol Downloaded：0: VHDL pi control，pid
Date : 2025-11-22 Size : 2kb User : 杨军
bpsk_spread_spectrum_modulator_demodulator Downloaded：0: code for bpsk spread spectrum modulator used in cdma ..
Date : 2025-11-22 Size : 8kb User : ANIL
handshake Downloaded：0: AMBA 3 AXI handshake protocol. Verilog platform. master and slave.
Date : 2025-11-22 Size : 192kb User : nodeity
counter Downloaded：0: -- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together
Date : 2025-11-22 Size : 1kb User : jgc
waveformgenerator Downloaded：0: The following information has been generated by Exemplar Logic -- and may be freely distributed and modified. -- -- Design name : smart_waveform -- -- Purpose : This design is a smart waveform generator. --
Date : 2025-11-22 Size : 1kb User : jgc

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