VHDL-FPGA-Verilog List Page 2609

VHDL-FPGA-Verilog list

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VHDL-0.1s-Timer Downloaded：0: The program completed the implementation in altera de2 0.1s under the new timer, which can be applied to the majority of sports events, a switch, pause start button, reset button.
Date : 2025-11-22 Size : 65kb User : koping
0.01s-Timer-designed-in-VHDL Downloaded：0: The design solution is to use VHDL language 0.01s timer, the program lists the detailed development process, and all source code, and although the simulation results
Date : 2025-11-22 Size : 686kb User : koping
DE2_SD_Card_Audio Downloaded：0: This demonstration show how to implement an SD Card Music Player on the DE2-70 board, in which the music files are stored in an SD card and the board can play the music files via its CD-quality audio DAC circuits.
Date : 2025-11-22 Size : 1.42mb User : vincechi
alarm Downloaded：0: used to create simple alarm system
Date : 2025-11-22 Size : 3kb User : elangov
Thsign Downloaded：0: The MTM bus on the main module VerilogHDL finite state machine design
Date : 2025-11-22 Size : 538kb User : ben3293
Altera_Cyclone_III Downloaded：0: Protel99 Library Altera_Cyclone_III
Date : 2025-11-22 Size : 70kb User : lyy
Altera_EPCS_Configuration_Device Downloaded：0: Protel99 Library Altera_EPCS_Configuration_Device
Date : 2025-11-22 Size : 4kb User : lyy
Reusabstem Downloaded：0: Reusable FPGA-based VXI System
Date : 2025-11-22 Size : 797kb User : car1850
FPGAystem Downloaded：0: FPGA and ARM-based digital storage oscilloscope Control System
Date : 2025-11-22 Size : 504kb User : car1850
DDS-baseenerator Downloaded：0: DDS-based design of multi-mode signal generator
Date : 2025-11-22 Size : 991kb User : dick1815
taxi-money Downloaded：0: Prepared using verilog achieve Taximeter daily accounting functions have
Date : 2025-11-22 Size : 2.85mb User : 陈凡
FPGA-basign Downloaded：0: FPGA-based drive control circuit of DMD Design
Date : 2025-11-22 Size : 1.35mb User : dick1815

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