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VHDL-FPGA-Verilog list
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DE2_70_NIOS_10
Downloaded:0
DE2-70 for the sopc builder for nios learning.
Date
: 2025-11-23
Size
: 1.97mb
User
:
刘慧
ocs-dpsk
Downloaded:0
Optical communications using the most top VPI simulation software platform, this program can be simulated to achieve the optical carrier suppressed-carrier RF systems in the differential phase shift keying (OCS-DPSK) mod
Date
: 2025-11-23
Size
: 5kb
User
:
Quartus-II-10.1-Handbook--Volume-3
Downloaded:0
the design of limited status in VHDL
Date
: 2025-11-23
Size
: 955kb
User
:
zz
scoreboard
Downloaded:1
Architecture implemented using verilog scoreboard algorithm, standard line
Date
: 2025-11-23
Size
: 145kb
User
:
王垚
xiaodou
Downloaded:0
Used 4x4 keyboard debounce, debounced keyboard operation as a major consideration, so shaking in Verilog consumer has an important role.
Date
: 2025-11-23
Size
: 1kb
User
:
changlingku
SAP1pond
Downloaded:0
SAP1 Using VHDL instead of presenting in Proteus
Date
: 2025-11-23
Size
: 577kb
User
:
CaST
FPGA-realise-the-SPI-code
Downloaded:0
Implementation of SPI with verilog program, also write the testbetch modelsim file, ideal for beginners to do SPI experiment, do it again, including quartus and modelsim simulation applications are the
Date
: 2025-11-23
Size
: 294kb
User
:
万鹏
signal
Downloaded:0
EP2C5Q208C8 verilog 50M m-sequences generated by dividing the crystal clock, you can choose from 10 clock--!
Date
: 2025-11-23
Size
: 1017kb
User
:
AM-FM-software-radio
Downloaded:0
FPGA development using AM, FM receiver paper, written by foreigners, I realized
Date
: 2025-11-23
Size
: 280kb
User
:
chenblue
51-clock
Downloaded:0
To 8951 microcontroller based clock system, including dynamic led display, 4 × 4 button
Date
: 2025-11-23
Size
: 61kb
User
:
yoyo
DS1307_I2C
Downloaded:0
Real time with ds1307
Date
: 2025-11-23
Size
: 548kb
User
:
Tuan
synplifypro[1]
Downloaded:0
This course introduces the new user to the SynplifyPro™ FPGA synthesis product. The topics covered will include:
Date
: 2025-11-23
Size
: 1.56mb
User
:
Chris
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