VHDL-FPGA-Verilog List Page 2049

VHDL-FPGA-Verilog list

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RS Downloaded：1: Design of the RS decoder source code-- Verilog HDL
Date : 2025-11-23 Size : 14kb User : 王垚
MIPS_cpu_verilog Downloaded：0: With lines of class MIPS CPU verilog source code
Date : 2025-11-23 Size : 18kb User : 王垚
4multiper8adder Downloaded：0: Adders and multipliers, including the so-ahead
Date : 2025-11-23 Size : 2kb User : 丁曦
cpu_verilog_vhdl Downloaded：0: Personal collection of the CPU core (with two 8051 documents, or12000) plus cpu design tutorials
Date : 2025-11-23 Size : 5.8mb User : 王垚
MIPS_CPU_OR2000 Downloaded：0: The development of the MIPS architecture CPU soft core OR2
Date : 2025-11-23 Size : 105kb User : 王垚
ahb_mas.tar Downloaded：0: its shows the ip of amba ahb master in vhdl
Date : 2025-11-23 Size : 23kb User : sachin
xp Downloaded：0: SCM, 96pin connector, 3366 potentiometer, 67148_AD_AD537, AD202 isolation amplifier, AD537, AD650SD voltage frequency, frequency-voltage converter, AD1671 high-speed AD, AD7376, 128-bit digital potentiometer, ADR440_441_
Date : 2025-11-23 Size : 9.87mb User : 牛谢宝
ahb_slave_latest.tar Downloaded：0: this shows the ip code for amba ahb slave in vhdl.
Date : 2025-11-23 Size : 5kb User : sachin
dma_ahb_latest.tar Downloaded：0: this shows the ip code for dma controller of amba ahb in vhdl.
Date : 2025-11-23 Size : 647kb User : sachin
change-8-to-1 Downloaded：0: Common examples of many hdl. And some examples of error-prone, this is my own summary of what
Date : 2025-11-23 Size : 3kb User : 宋俊福
GPIOsimulateUART Downloaded：0: This code is to use the GPIO port 8051 to simulate an ordinary serial port
Date : 2025-11-23 Size : 354kb User : 余金锁
suzimiaobiao Downloaded：0: there is function of clock,it very useful
Date : 2025-11-23 Size : 93kb User : 宋俊福

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