VHDL-FPGA-Verilog List Page 2046

VHDL-FPGA-Verilog list

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mux41 Downloaded：1: VHDL language to achieve 4 to 1 channel, in the FPGA to achieve.
Date : 2025-11-23 Size : 1kb User : 汪云
FPGAxinlingyinfangzhen Downloaded：0: FPGA-based signaling tone generation process, including dial tone, busy tone, ring tones, etc.
Date : 2025-11-23 Size : 2.03mb User : 于风
bsconvert Downloaded：0: FPGA-based string and data conversion procedures, can be 8-bit serial data into 8-bit parallel data, or the 8-bit 8-bit parallel data into serial data
Date : 2025-11-23 Size : 223kb User : 于风
sqrt-base-on-fpga Downloaded：0: An improved non-recovery of the remainder of the square root algorithm (non- restoring square- root algorithm) are discussed and applied based on the IEEE 754 standard 32-bit floating point format in the square root to a
Date : 2025-11-23 Size : 123kb User :
8B10B_decode Downloaded：0: 8b/10b encoding and decoding described the detailed proce
Date : 2025-11-23 Size : 75kb User :
Timing_constraints(Xilinx) Downloaded：0: Details of the timing of FPGA logic design, timing set to note briefly the main points and key, set up time and hold time and so on
Date : 2025-11-23 Size : 782kb User :
FPGA-global-clk-design- Downloaded：0: FPGA' s global clock should be divided out from the crystal, the frequency of the most original. Other needs of the various frequencies are based on the use of this frequency PLL or other means to get because many nee
Date : 2025-11-23 Size : 2kb User :
FPGA_IO Downloaded：0: Experience counts- especially when engineering the right FPGA solution. And with more than 50 years of experience, Acromag can help you reduce your costs and increase your productivity.
Date : 2025-11-23 Size : 1.38mb User :
I2C Downloaded：0: The I2C verilog implementation, validation can be used, need can be downloaded
Date : 2025-11-23 Size : 3kb User :
my_FIFO Downloaded：0: Verilog implementation of FIFO successfully validated, the good need can be downloaded
Date : 2025-11-23 Size : 1kb User :
my_VGA Downloaded：0: VGA display driven by the FPGA, through validation, need can be downloaded. verilog implementation
Date : 2025-11-23 Size : 1kb User :
main Downloaded：0: This is an ADS environment, the successful commissioning of the above in the LPC2132 UART interrupt a run on the program
Date : 2025-11-23 Size : 1kb User : 曹小强

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