Introduction - If you have any usage issues, please Google them yourself
An improved non-recovery of the remainder of the square root algorithm (non- restoring square- root algorithm) are discussed and applied based on the IEEE 754 standard 32-bit floating point format in the square root to a FPGA as the carrier, to achieve the basic circuit operation. Evolution of several existing algorithms have been reviewed, analyzed their advantages and disadvantages of the proposed improvements do not restore the remainder of the modular square root algorithm and key circuit design ideas, and analyzed the results of simulation and logic synthesis, that the arithmetic operations faster and take up very little resources characteristics.