SAP1 Using VHDL instead of presenting in Proteus

SAP1\.lso
....\ALU.prj
....\ALU.stx
....\ALU.vhd
....\ALU.xst
....\BCD_decoder.prj
....\BCD_decoder.spl
....\BCD_decoder.stx
....\BCD_decoder.sym
....\BCD_decoder.vhd
....\BCD_decoder.xst
....\CM.cmd_log
....\CM.lso
....\CM.prj
....\CM.syr
....\CM.vhd
....\CM.xst
....\CM_summary.html
....\CU.cmd_log
....\CU.lso
....\CU.ngc
....\CU.ngr
....\CU.prj
....\CU.stx
....\CU.syr
....\CU.vhd
....\CU.xst
....\CU_summary.html
....\gen_CLK250Hz.prj
....\gen_CLK250Hz.stx
....\gen_CLK250Hz.vhd
....\gen_CLK250Hz.xst
....\gen_CLK250Hz_vhdl.prj
....\ID.prj
....\ID.stx
....\ID.vhd
....\ID.xst
....\IR.vhd
....\JK-FF.vhd
....\JKFF.cmd_log
....\JKFF.lso
....\JKFF.prj
....\JKFF.stx
....\JKFF.syr
....\JKFF.xst
....\JKFF_summary.html
....\JKFF_vhdl.prj
....\MAR.prj
....\MAR.stx
....\MAR.vhd
....\MAR.xst
....\MultiplexerDraw.prj
....\MultiplexerDraw.spl
....\MultiplexerDraw.stx
....\MultiplexerDraw.sym
....\MultiplexerDraw.vhd
....\MultiplexerDraw.xst
....\MultiplexerDraw_summary.html
....\netgen\synthesis\OutputRegister_synthesis.nlf
....\......\.........\OutputRegister_synthesis.v
....\......\.........\Registor_IC_synthesis.nlf
....\......\.........\Registor_IC_synthesis.v
....\OutputRegister.bld
....\OutputRegister.lfp
....\OutputRegister.ncd
....\OutputRegister.ngc
....\OutputRegister.ngd
....\OutputRegister.ngr
....\OutputRegister.pad
....\OutputRegister.par
....\OutputRegister.pcf
....\OutputRegister.spl
....\OutputRegister.sym
....\outputregister.twr
....\outputregister.twx
....\OutputRegister.ucf
....\OutputRegister.unroutes
....\OutputRegister.vhd
....\OutputRegister.xpi
....\OutputRegister_map.mrp
....\OutputRegister_map.ncd
....\OutputRegister_map.ngm
....\OutputRegister_pad.csv
....\OutputRegister_pad.txt
....\OutputRegister_prev_built.ngd
....\OutputRegister_summary.html
....\OutputRegister_usage.xml
....\PC.vhd
....\pepExtractor.prj
....\PROM.prj
....\PROM.stx
....\PROM.vhd
....\PROM.xst
....\RC.cmd_log
....\RC.lso
....\RC.ngc
....\RC.ngr
....\RC.prj
....\RC.stx
....\RC.syr

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