Architecture implemented using verilog scoreboard algorithm, standard line

scoreboard\add_sub_comp.v
..........\add_sub_comp.v.bak
..........\control.v
..........\control.v.bak
..........\cpu_top.v
..........\cpu_top.v.bak
..........\define.v
..........\define.v.bak
..........\DIV_ALU.v
..........\DIV_ALU.v.bak
..........\IF_stage.v
..........\IF_stage.v.bak
..........\jump_comp.v
..........\jump_comp.v.bak
..........\LD_ST.v
..........\LD_ST.v.bak
..........\mul.v
..........\mul.v.bak
..........\RAM.v
..........\RAM.v.bak
..........\registers.v
..........\scoreboard.cr.mti
..........\scoreboard.mpf
..........\work\@a@d@d_@a@l@u\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\.control\verilog.asm
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\.d@i@v_@a@l@u\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\.i@f_stage\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\.l@d_@s@t\verilog.asm
..........\....\.........\_primary.dat
..........\....\.........\_primary.vhd
..........\....\.m@e@m_@a@l@u\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\...u@l_@a@l@u\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\.r@a@m\verilog.asm
..........\....\......\_primary.dat
..........\....\......\_primary.vhd
..........\....\add_sub_comp\verilog.asm
..........\....\............\_primary.dat
..........\....\............\_primary.vhd
..........\....\control\verilog.asm
..........\....\.......\_primary.dat
..........\....\.......\_primary.vhd
..........\....\.pu_top\verilog.asm
..........\....\.......\_primary.dat
..........\....\.......\_primary.vhd
..........\....\jump_comp\verilog.asm
..........\....\.........\_primary.dat
..........\....\.........\_primary.vhd
..........\....\mul_comp\verilog.asm
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\registers\verilog.asm
..........\....\.........\_primary.dat
..........\....\.........\_primary.vhd
..........\....\_info
..........\....\@a@d@d_@a@l@u
..........\....\@control
..........\....\@d@i@v_@a@l@u
..........\....\@i@f_stage
..........\....\@l@d_@s@t
..........\....\@m@e@m_@a@l@u
..........\....\@m@u@l_@a@l@u
..........\....\@r@a@m
..........\....\add_sub_comp
..........\....\control
..........\....\cpu_top
..........\....\jump_comp
..........\....\mul_comp
..........\....\registers
..........\work
scoreboard

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