VHDL-FPGA-Verilog List Page 1808

VHDL-FPGA-Verilog list

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verilog-UART-Controler Downloaded：0: Using the UART controller verilog language, including sending and receiving part, the baud rate is adjustable.
Date : 2025-09-17 Size : 112kb User : 张秋光
verilog-rom Downloaded：0: ROM module verilog language code.
Date : 2025-09-17 Size : 89kb User : 张秋光
verilog-CAN-Controler Downloaded：0: Use the CAN controller verilog language code.
Date : 2025-09-17 Size : 44kb User : 张秋光
FPGA-code--USB-light-up-LED Downloaded：0: a FPGA code used to a test about USB light up LED
Date : 2025-09-17 Size : 140kb User : 上善若水
CPU Downloaded：0: 4 and 8-bit, 8 operations, QUARTUS simple processors, can run on the Quartus
Date : 2025-09-17 Size : 6.26mb User : 朱源文
final-design Downloaded：0: make a left shifting register in verilog HDL
Date : 2025-09-17 Size : 1.32mb User : 陈静波
clock Downloaded：0: Multi-function digital clock 24 hours to strike the alarm clock on the hour function when the reset function, etc
Date : 2025-09-17 Size : 11kb User : 韩延罡
clock--the-end Downloaded：0: Multi-function digital clock 24 hours to strike the alarm clock on the hour function when the reset function, etc
Date : 2025-09-17 Size : 2kb User : 韩延罡
scrambler-wimax Downloaded：0: This package contains synthesizable VHDL codes for scramber/descrambler module for IEEE 802.16 WiMAX PHY layer.
Date : 2025-09-17 Size : 1kb User : zpatel
Lcd Downloaded：0: lcd interface with PIC microocntroller
Date : 2025-09-17 Size : 30kb User : raj
qiduanxianshiyima Downloaded：0: Using decode program FPGA/CPLD realized in hexadecimal number decoding display. Through the EDA principle diagram design method using the prim library 7448 chips for 7 period of decoding display
Date : 2025-09-17 Size : 50kb User : 韩延罡
38yimaqi Downloaded：0: Learning design a 3/8 decoder experiments, the board validation 2. Learn to use VHDL language to logical design input 3. Learning design simulation tools using methods
Date : 2025-09-17 Size : 358kb User : 韩延罡

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