make a left shifting register in verilog HDL

final design\74x151.v.bak
............\AritL.v
............\AritL.v.bak
............\AritL_tst.v
............\db\finaldesign.analyze_file.qmsg
............\..\finaldesign.asm.qmsg
............\..\finaldesign.atom.rvd
............\..\finaldesign.cbx.xml
............\..\finaldesign.cmp.bpm
............\..\finaldesign.cmp.cdb
............\..\finaldesign.cmp.ecobp
............\..\finaldesign.cmp.hdb
............\..\finaldesign.cmp.kpt
............\..\finaldesign.cmp.logdb
............\..\finaldesign.cmp.rdb
............\..\finaldesign.cmp.tdb
............\..\finaldesign.cmp0.ddb
............\..\finaldesign.cmp_merge.kpt
............\..\finaldesign.db_info
............\..\finaldesign.eco.cdb
............\..\finaldesign.eda.qmsg
............\..\finaldesign.fit.qmsg
............\..\finaldesign.fnsim.hdb
............\..\finaldesign.fnsim.qmsg
............\..\finaldesign.hier_info
............\..\finaldesign.hif
............\..\finaldesign.lpc.html
............\..\finaldesign.lpc.rdb
............\..\finaldesign.lpc.txt
............\..\finaldesign.map.bpm
............\..\finaldesign.map.cdb
............\..\finaldesign.map.ecobp
............\..\finaldesign.map.hdb
............\..\finaldesign.map.kpt
............\..\finaldesign.map.logdb
............\..\finaldesign.map.qmsg
............\..\finaldesign.map_bb.cdb
............\..\finaldesign.map_bb.hdb
............\..\finaldesign.map_bb.logdb
............\..\finaldesign.pre_map.cdb
............\..\finaldesign.pre_map.hdb
............\..\finaldesign.rpp.qmsg
............\..\finaldesign.rtlv.hdb
............\..\finaldesign.rtlv_sg.cdb
............\..\finaldesign.rtlv_sg_swap.cdb
............\..\finaldesign.sgate.rvd
............\..\finaldesign.sgate_sm.rvd
............\..\finaldesign.sgdiff.cdb
............\..\finaldesign.sgdiff.hdb
............\..\finaldesign.sim.cvwf
............\..\finaldesign.sim.hdb
............\..\finaldesign.sim.qmsg
............\..\finaldesign.sim.rdb
............\..\finaldesign.simfam
............\..\finaldesign.sld_design_entry.sci
............\..\finaldesign.sld_design_entry_dsc.sci
............\..\finaldesign.syn_hier_info
............\..\finaldesign.tan.qmsg
............\..\finaldesign.tis_db_list.ddb
............\..\finaldesign.tmw_info
............\..\finaldesign_global_asgn_op.abo
............\..\prev_cmp_finaldesign.asm.qmsg
............\..\prev_cmp_finaldesign.eda.qmsg
............\..\prev_cmp_finaldesign.fit.qmsg
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............\..\prev_cmp_finaldesign.qmsg
............\..\prev_cmp_finaldesign.sim.qmsg
............\..\prev_cmp_finaldesign.tan.qmsg
............\..\wed.wsf
............\finaldesign.asm.rpt
............\finaldesign.done
............\finaldesign.dpf
............\finaldesign.eda.rpt
............\finaldesign.fit.rpt
............\finaldesign.fit.smsg
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............\finaldesign.flow.rpt
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............\finaldesign.map.summary
............\finaldesign.pin
............\finaldesign.qpf
............\finaldesign.qsf
............\finaldesign.sim.rpt
............\finaldesign.tan.rpt
............\finaldesign.tan.summary
............\finaldesign_nativelink_simulation.rpt
............\incremental_db\compiled_partitions\finaldesign.root_partition.cmp.atm
............\..............\...................\finaldesign.root_partition.cmp.dfp
............\..............\...................\finaldesign.root_partition.cmp.hdbx
............\..............\...................\finaldesign.root_partition.cmp.kpt
............\..............\...................\finaldesign.root_partition.cmp.logdb
............\..............\...................\finaldesign.root_partition.cmp.rcf
............\..............\...................\finaldesign.root_partition.map.atm
............\..............\...................\finaldesign.root_partition.map.dpi
............\..............\...................\finaldesign.root_partition.map.hdbx
............\..............\...................\finaldesign.root_partition.map.kpt
............\..............\README
............\modelsim.i

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