VHDL-FPGA-Verilog List Page 1804

VHDL-FPGA-Verilog list

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verilog_learn Downloaded：0: Verilog for beginners to learn a good example, may be useful for beginners, are classic examples
Date : 2025-09-16 Size : 2.46mb User :
des_3 Downloaded：0: 3DES encryption and decryption algorithms for the verilog implementation has been tested for learning the implementation of 3DES encryption and decryption process is useful
Date : 2025-09-16 Size : 11kb User :
UART Downloaded：0: C8051F410 microcontroller UART application, simple and understandable in compile keil
Date : 2025-09-16 Size : 4kb User : 王绿飞
move Downloaded：0: VGA mobile striped design. In order to show more images, with external ROM replace the FPGA internal ROM
Date : 2025-09-16 Size : 24kb User : yishuihan
sdram_access Downloaded：0: sdram controller,vhdl program
Date : 2025-09-16 Size : 711kb User : wanggt
STM32108PKT-I2C-E2PROM Downloaded：0: The routine use I2C2 to read and write M24C02. The routine use check the status of the I2C bus mode, the I2C devices to make access to reliable and According to the I2C protocol, read and write M24C02, SysTick timeout fo
Date : 2025-09-16 Size : 29kb User : zhangxuezhi
SIMPLE-ALU.docx Downloaded：0: SIMPLE ALU CODE IN VHDL
Date : 2025-09-16 Size : 169kb User : SATYA
spartan_LCD Downloaded：0: Realize the Spartan-3 E LCD display driver, can pass LCD observation data changes
Date : 2025-09-16 Size : 1kb User : 乔子良
I2C_vhdl Downloaded：0: IMPORTANT NOTE: This design uses the I2C SCL signal as a clock. This requires that the SCL signal have clean, fast edges on both the rising and falling edges of this signal. Slow rise and fall times on this signal can s
Date : 2025-09-16 Size : 830kb User : vijendra pal
manchester_verilog Downloaded：0: This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
Date : 2025-09-16 Size : 10kb User : vijendra pal
manchester_vhdl Downloaded：0: This design is targeted to the XCR3064XL-7VQ100C CoolRunner CPLD. This is a 3V, 64 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
Date : 2025-09-16 Size : 11kb User : vijendra pal
spi_cpld_vhdl Downloaded：0: The CoolRunner-II "Confuguring Xilinx FPGAs with SPI Flash Memories using CoolRunner-II CPLDs" reference design is based upon the STMicroelectronics SPI Flash memory M25P20. This design can be easily modified to support
Date : 2025-09-16 Size : 431kb User : vijendra pal

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