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VHDL-FPGA-Verilog list
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laboratory-10
Downloaded:0
this is a file for lab10 of DE2,you can use this to learn how to design a processor
Date
: 2025-09-17
Size
: 40kb
User
:
pei
shenfaqi
Downloaded:0
Design a divider circuit, type 8- bit of the dividend A and divisor B, output of business Q = A/B and the remainder R.
Date
: 2025-09-17
Size
: 1kb
User
:
yc
qudoudong
Downloaded:0
Many buttons to dither circuit VHDL source, the number of key parameter, each key, the call to the treatment of the above modules:
Date
: 2025-09-17
Size
: 1kb
User
:
韩延罡
random1
Downloaded:0
Random binary sequence generator using four flip-flops. It does not require any external input except clock.
Date
: 2025-09-17
Size
: 1kb
User
:
zpatel
SIPO-PISO-register
Downloaded:0
Package contains two VHDL module: one for serial in and parallel out (SIPO) register and other for parallel in and serial out (PISO) register.
Date
: 2025-09-17
Size
: 1kb
User
:
zpatel
convol_enc
Downloaded:0
VHDL code for convolution encoder for wimax PHY layer. This design also has control to add controlled amount of noise in encoded output.
Date
: 2025-09-17
Size
: 1kb
User
:
zpatel
clock-divider
Downloaded:0
VHDL code for clock divider circuit. There are two modules: one output divide by 4 and other outputs divide by 6
Date
: 2025-09-17
Size
: 1kb
User
:
zpatel
mapper-demapper
Downloaded:0
Contains two VHDL files: one for mapper and other for demapper. Their design is as per 802.11b standard for WiFi
Date
: 2025-09-17
Size
: 1kb
User
:
zpatel
VHDLkechengsheji
Downloaded:0
This a curriculum design VHDL contains three topics water lights answer two answer four just finished Chuan-up share
Date
: 2025-09-17
Size
: 52kb
User
:
李之如
I2C-
Downloaded:0
The address of a single reading and writing the I2C bus of the data bytes (eight) way to transmit, send each device sends a byte after, the clock pulse 9 of the data bus during release, the receiver send a ACK (the data
Date
: 2025-09-17
Size
: 28kb
User
:
叶小玲
led-8-display
Downloaded:0
matrax keyboard and led display program C
Date
: 2025-09-17
Size
: 1kb
User
:
tang
chaoshengbo
Downloaded:0
The top file based on FPGA
Date
: 2025-09-17
Size
: 2.1mb
User
:
陈忠元
«
1
2
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.02
.03
.04
.05
.06
1807
.08
.09
.10
.11
.12
...
4310
»
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