VHDL-FPGA-Verilog List Page 1728

VHDL-FPGA-Verilog list

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SGvga Downloaded：0: Based on the System Generator Xilinx FGPA VGA display module, the plate Nexys ™ 3 the Spartan-6 FPGA Board directly. Bit file into the conduct.
Date : 2025-09-15 Size : 1.17mb User : 张文龙
uar_bmp Downloaded：0: a color picture can be displayed in LCD though UART.
Date : 2025-09-15 Size : 3kb User : 熊杰
CPU Downloaded：0: ten instruction simply cpu,it can write and read data to other equipment
Date : 2025-09-15 Size : 1.05mb User : 萝卜
traffic-light Downloaded：0: His writing the code with VHDL, realize the intersection traffic light control. And can the digital display different lamp shows the time countdown.
Date : 2025-09-15 Size : 1kb User : chenhenhao
FIFO2 Downloaded：0: Using Verilog language HDL FIFO memory source file
Date : 2025-09-15 Size : 1.41mb User : 王浩宇
digital_clock_top Downloaded：0: VHDL realize the development of digital clock , the platform is DE-2 board,which can Regulation time and minite
Date : 2025-09-15 Size : 98kb User : 张恒毅
oc_i2c_masterI2CIP Downloaded：0: oc_i2c_master
Date : 2025-09-15 Size : 190kb User : bearfar
SRC Downloaded：0: Pipelined cpu top-level module verilog source code, and the ALU sub-module source code
Date : 2025-09-15 Size : 2kb User : 吴慧
elevltor Downloaded：0: -The controller of three 8-level elevators, designed with Verilog. The design is detailedly represented in the DOC as well as the source code.
Date : 2025-09-15 Size : 628kb User : shenge
POC Downloaded：0: A parallel output controller
Date : 2025-09-15 Size : 48kb User : qinhai
booth Downloaded：0: BOOTH VHDL!
Date : 2025-09-15 Size : 4kb User : 王瀚颖
cpu Downloaded：0: FPGA Implementation of a CPU, RAM, ROM, function, design is more complete
Date : 2025-09-15 Size : 1.21mb User : shenhaoxing

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