VHDL-FPGA-Verilog List Page 1724

VHDL-FPGA-Verilog list

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Codificador_Binario_Y_Gray Downloaded：0: Encoder gray and binary 8 bits
Date : 2025-09-15 Size : 3kb User : tolima
Cuantificador Downloaded：0: Cuantificador con 3 bits (Niveles graduables)
Date : 2025-09-15 Size : 1kb User : tolima
Sinusoidal Downloaded：0: sine generator in rom with 512 points.
Date : 2025-09-15 Size : 1kb User : tolima
Frecdiv Downloaded：0: Frecuency divisor with 3 bits of variable.
Date : 2025-09-15 Size : 1kb User : tolima
tren_de_pulsos Downloaded：0: Generator of pulse train to 50MHz.
Date : 2025-09-15 Size : 1kb User : tolima
subtractor5 Downloaded：0: 5 hex subtractor
Date : 2025-09-15 Size : 1kb User : naive
happy5 Downloaded：0: game for ssd: ssd lit up in clockwise
Date : 2025-09-15 Size : 249kb User : 汤日方
REC_C8 Downloaded：0: NIOSii CPU
Date : 2025-09-15 Size : 24.93mb User : xiaoqp
div_fp Downloaded：0: Enter any frequency can be realized to achieve the 1-15 arbitrary duty cycle 50 of the sub-frequency
Date : 2025-09-15 Size : 352kb User : taocheng
clock Downloaded：0: Electronic clock design Electronic clock design
Date : 2025-09-15 Size : 3kb User : 叶淼胤
cpu-and-ram Downloaded：0: This is a simple memory write VHDL CPU design, does not involve the assembly line design, simply use the ram in QUARTUES
Date : 2025-09-15 Size : 1.2mb User : 郭雅娟
the-strong-cpu-design Downloaded：0: Enhanced CPU design, with the PC pointer memory write VHDL language, non-pipelined design to achieve binary bright light cycle
Date : 2025-09-15 Size : 1.54mb User : 郭雅娟

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