VHDL-FPGA-Verilog List Page 1730

VHDL-FPGA-Verilog list

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ADC12-sampling-experiment Downloaded：0: DC1 work for 14 Mhz clock, use ADC1 channel 8 to continuous conversion, and use the DMA to convert data transmission, and in the TFT To convert data on real-time display
Date : 2025-09-15 Size : 874kb User : 荣德国
FPGA-ET Downloaded：0: DDS generator advanced programe
Date : 2025-09-15 Size : 141kb User : dongjun
vgaball Downloaded：0: Written by VHDL balls of the game code, VGA display, module to the VGA controller have very good portability
Date : 2025-09-15 Size : 3.68mb User : wu
Ultra-9-17 Downloaded：0: The ultrasonic flowmeter sampling control part of the VHDL source code, based on xilinx s spartan3
Date : 2025-09-15 Size : 1.67mb User : aweawfg
IEEE-Standard-for-SystemVerilog Downloaded：0: This a SystemVerilog standard are welcome to download
Date : 2025-09-15 Size : 5.87mb User : 钟普
synopsys_verification Downloaded：0: This is synposys SystemVerilog using the wizard
Date : 2025-09-15 Size : 654kb User : 钟普
verilogCRC32 Downloaded：0: The encode of CRC32 with 32bit-inputs based on verilog, and according encode of testbench
Date : 2025-09-15 Size : 2kb User : maxwell
24stimer Downloaded：0: basketball 24s timer code of verilog
Date : 2025-09-15 Size : 64kb User : maxwell
ICM7242 Downloaded：0: failed to translate
Date : 2025-09-15 Size : 247kb User : 小贾
pinlv01 Downloaded：0: VHDL frequent
Date : 2025-09-15 Size : 12.16mb User : 朱曦
base-on-FPGA-AES-addkey-design Downloaded：0: introduce design tool,language and core of AES which base on FPGA,and AES hardware design.
Date : 2025-09-15 Size : 2.08mb User : 邱绿
data_syn_check_47 Downloaded：0: Frame synchronous search,Replace MPEG-2 TS stream by using the control data
Date : 2025-09-15 Size : 29kb User : 杨明

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