VHDL-FPGA-Verilog List Page 1734

VHDL-FPGA-Verilog list

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MAXPPLUS-II Downloaded：0: This about using the MAX+ PLUS II schematic design methodology for FPGA design tutorials, easy Quick Start.
Date : 2025-09-15 Size : 781kb User : 王红卫
MAXPLUS_Usage Downloaded：0: The rapid entry-level tutorial on the use of Altera Corporation the MaxPlus II software, it is suitable for ready to use the MaxPlus II FPGA design friends.
Date : 2025-09-15 Size : 1002kb User : 王红卫
quartusHand2Hand Downloaded：0: FPGA design has become increasingly popular to use Quartus for Altera Corporation, this tutorial is to help a friend in need into the Quartus design door key.
Date : 2025-09-15 Size : 1.78mb User : 王红卫
VHDL_MII_MAC Downloaded：0: verilog HDL， MII，ethernet，hope helpful to you。
Date : 2025-09-15 Size : 124kb User : wh
account Downloaded：0: Telephone billing program, showing the balance of the card, the time of the call balance too came from the alarm signal. Automatically when the alarm time is too long to cut off the call signal.
Date : 2025-09-15 Size : 16kb User : happy
traffic Downloaded：0: CLK: synchronized clock EN: Enable signal is 1, then the controller starts to work LAMPA: control the direction A four lamp light off which, LAMPA0, ~ LAMPA3, respectively, to control the direction of A
Date : 2025-09-15 Size : 314kb User : happy
fir-filter Downloaded：0: 11 order of fir digital filter verilog programming, linear phase, the coefficient quantization
Date : 2025-09-15 Size : 58kb User : happy
clock Downloaded：0: clk: standard clock signal, in this case, the frequency of 4Hz clk_1k: generate the alarm sound, chime sound clock signal, in this case the frequency of 1024Hz mode: Functional control signal 0: Chronograph function 1: T
Date : 2025-09-15 Size : 480kb User : happy
serial Downloaded：0: The function of this module is to verify the basic serial communication and PC. Need to be installed on a PC with a serial debugging tools to verify the functionality of the program. The program implements a send and rec
Date : 2025-09-15 Size : 55kb User : happy
ledwater Downloaded：0: Marquee experiment: the use of the counter in turn lights up the LED lights, a variety of dynamic effects.
Date : 2025-09-15 Size : 145kb User : happy
tcp_tiaoshi Downloaded：0: Fpga_sopc_enc28j60_tcp_ip_ test, the source code packets, I test through!
Date : 2025-09-15 Size : 13.69mb User : bangmin hu
ov7670 Downloaded：1: Fpga_sopc_ov7670_ driver, contain hardware circuit.
Date : 2025-09-15 Size : 15.12mb User : bangmin hu

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