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VHDL-FPGA-Verilog list
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FPGA-using-for-SDR
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FPGA SDR
Date : 2025-11-22 Size : 22.06mb User : luhb
xiyiji
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Design are relatively complete application system, including at least three module (timer, a serial port, keyboard, digital tube, liquid crystal display, sensor module conversion, PWM, etc)
Date : 2025-11-22 Size : 12kb User : 孤独的小飞侠
main
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the main program of series of machxo。
Date : 2025-11-22 Size : 3kb User : 小庆
master-for-hsdpa
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master for design physical layer of vhdl of fpga
Date : 2025-11-22 Size : 1.17mb User : uogy
ARM_kernel_verilogHDL
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This the ARM core processor verilogHDL code, is a soft core.
Date : 2025-11-22 Size : 37kb User : lipuran
hufmann
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Huffman coding for JPEG and MPEG files.
Date : 2025-11-22 Size : 5kb User : Dim
phase
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Time interval measurement code
Date : 2025-11-22 Size : 20kb User : 陈瑞昊
divide
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divide module, the division function. The module is written in Verilog, compression bag, including the design process and testing process Sequence (testbench).
Date : 2025-11-22 Size : 31kb User : 周狩猎
led
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The program is written in Verilog hardware circuit description of the procedures led the use of the program can be simulated and tested.
Date : 2025-11-22 Size : 16kb User : 周狩猎
TIMER1
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TIMER-1 : 定时器上溢。 TIMER-2 : 强置输出模式。 TIMER-3 : 输出比较模式。 TIMER-4 : PWM1模式。 TIMER-5 : 输入捕获模式(结果硬件仿真观察)。 TIMER-6 : PWM输入模式。 TIMER-7 : 单脉冲模式。 TIMER-8 : TIMER2作为TIMER3的分频器,即TIMER3的时钟由TIMER2提供。 TIMER-9 : TIMER2使能TIMER3(时钟都用内部时钟，两
Date : 2025-11-22 Size : 3.77mb User : 陈立
TIMER2
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TIMER-1 : 定时器上溢。 TIMER-2 : 强置输出模式。 TIMER-3 : 输出比较模式。 TIMER-4 : PWM1模式。 TIMER-5 : 输入捕获模式(结果硬件仿真观察)。 TIMER-6 : PWM输入模式。 TIMER-7 : 单脉冲模式。 TIMER-8 : TIMER2作为TIMER3的分频器,即TIMER3的时钟由TIMER2提供。 TIMER-9 : TIMER2使能TIMER3(时钟都用内部时钟，两
Date : 2025-11-22 Size : 4.38mb User : 陈立
vertosysc
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verilog to systemc
Date : 2025-11-22 Size : 5kb User : jason
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