VHDL-FPGA-Verilog List Page 1625

VHDL-FPGA-Verilog list

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mealy Downloaded：0: mealy state machine description, there are detailed steps and source code
Date : 2025-09-14 Size : 213kb User : 文苗
DDS Downloaded：0: DDS single sinx f=1-50Mhz
Date : 2025-09-14 Size : 2.17mb User : huawei
68013A_BULK_TRANS Downloaded：0: CY68013A asynchronous BULK transmission model, in strict accordance with the temporal description to read and write, read and write to the FIFO implementation, perfect function.
Date : 2025-09-14 Size : 216kb User : fairy
counter Downloaded：0: a decoder a deciph
Date : 2025-09-14 Size : 44kb User : 刘轨痕
FPGA Downloaded：0: A digital frequency synthesizer FPGA implementation technology
Date : 2025-09-14 Size : 308kb User : 陆鹏
4-5 Downloaded：0: Four to five homes in judging circuit, the input to the 8421BCD code, when the distance is greater than or equal to 5, judging circuit outputs of 1, instead of 0.
Date : 2025-09-14 Size : 30kb User : 华佗
verilog Downloaded：0: Matrix not away with verilog keyboard shake language, file introduction and clear. Easy to see all and modification.
Date : 2025-09-14 Size : 3kb User : 高炼
FPGA-digital-clock-design Downloaded：0: This the design of FPGA-based multi-function digital clock. A paper, look at it.
Date : 2025-09-14 Size : 485kb User : 俞佳慧
2 Downloaded：0: VHDL one hundred-bit counter counting function, suitable for beginners to learn
Date : 2025-09-14 Size : 277kb User : li
testbench(xilinx) Downloaded：0: The Testbench not only to generate incentives to input, verify that the response is output. Of course, can only produce Incentive, and then the waveform by the waveform window by artificial means to verify, this method i
Date : 2025-09-14 Size : 88kb User : 宏红
4-_add Downloaded：0: The level 4 water way QuanJia 8 bits for speech that described VHDL
Date : 2025-09-14 Size : 248kb User : 郭少华
4-a-string-and-converter Downloaded：0: 4 a string and converter VHDL language describe
Date : 2025-09-14 Size : 179kb User : 郭少华

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