VHDL-FPGA-Verilog List Page 1622

VHDL-FPGA-Verilog list

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cp2102 Downloaded：0: usb to uart chip cp2102 manual
Date : 2025-09-14 Size : 338kb User : gaosong
UART Downloaded：0: uart driver module development board sep4020, serial 0, serial debugging assistant prochip
Date : 2025-09-14 Size : 320kb User : 邹甬
main Downloaded：0: IR decoding LCD1602 liquid crystal display can display the already successful infrared coding decoding
Date : 2025-09-14 Size : 3kb User : liufuzhi
PWM Downloaded：0: pwm module sep4020 development board driver to sound the buzzer sounded, with the pwm waveform
Date : 2025-09-14 Size : 303kb User : 邹甬
a Downloaded：0: mips single cycle verilog code for add,sub,bne,slt,lw,sw,xori instructions
Date : 2025-09-14 Size : 8kb User : nhan
TEST1 Downloaded：0: Use DCM module in Xilinx FPGA.Creat a IP module to do it.
Date : 2025-09-14 Size : 569kb User : dxf
Manchester-Encoding-Verilog Downloaded：0: THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON
Date : 2025-09-14 Size : 8kb User : liyapei
IFSPCI_IP Downloaded：1: Source of the PCI5054 C, mode, PLX 9054 chip as an interface between the pci bus and local bus pass information. The PCI card is the use of this feature plx9054, peripherals and pc machine interface control circuit, to b
Date : 2025-09-14 Size : 998kb User : liyapei
PCI9054 Downloaded：0: This article describes a design based on the PCI interface, 500 MHz high-speed data acquisition system.The system uses high-speed FPGA and high-capacity memory buffering and storage of vast amounts of data in high-speed
Date : 2025-09-14 Size : 253kb User : liyapei
A-Novel-Coordinated-Control-Strategy-for-Improvin Downloaded：0: A Novel Coordinated Control Strategy for Improving
Date : 2025-09-14 Size : 464kb User : meysam
eda Downloaded：0: Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six cou
Date : 2025-09-14 Size : 33kb User : 王丽丽
Filter Downloaded：0: VHDL and sopc written oscilloscope program, you can compile, you can perform
Date : 2025-09-14 Size : 24.73mb User : li

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