VHDL-FPGA-Verilog List Page 1621

VHDL-FPGA-Verilog list

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Process_Algebra_www.softarchive.net Downloaded：0: Research towards meeting the higher demands for higher data rates was the main reason for the birth of an evolution technology towards the 4th generation mobile communication systems. This evolution to the current 3rd ge
Date : 2025-09-14 Size : 3.47mb User : Dang Dung
2048Mb_ddr2_verilog_model Downloaded：0: DDR2 Verilog model, and used to verify the DDR2 Controller.
Date : 2025-09-14 Size : 2.51mb User : 天空
ZZZZ Downloaded：0: China robot competition arena design, mainly for11 years of robot competitions, reference
Date : 2025-09-14 Size : 1kb User : 王鹏
1 Downloaded：0: vhdl bpsk fpga dpsk module psk(clk,clr,fcw,angle,M,EN,psk_output) input[31:0]fcw //载波频率 input[9:0]angle //载波相位 input clk,clr input M,EN //M为
Date : 2025-09-14 Size : 92kb User : yanchao
hanzi Downloaded：0: Is mainly based on the FPGA man display, extraction of Chinese characters library, service to other programs
Date : 2025-09-14 Size : 1kb User : 王鹏
8255 Downloaded：0: Experiment of Microcomputer a 8255 chip, the function of the traffic lights, and switch controls the LED lights Experimental ASM file written in assembly language
Date : 2025-09-14 Size : 86kb User : 林辉
DSO_Project Downloaded：0: digital oscilloscope fpga source
Date : 2025-09-14 Size : 1.37mb User : myname
quartus Downloaded：0: rs encoding the main program
Date : 2025-09-14 Size : 29kb User : 葫芦
vhdl11 Downloaded：0: keyboard intefacing program
Date : 2025-09-14 Size : 1kb User : siddharth815
FIFO Downloaded：0: Write FIFO Verilog
Date : 2025-09-14 Size : 513kb User : 郝继龙
TDM Downloaded：0: matlab in Applied Communication Theory, TDM emulation, hope that we can useful!
Date : 2025-09-14 Size : 516kb User : 谢展芬
6fenpin Downloaded：0: The inside of the graduation design a module, mainly realizes the clock frequency function of six points
Date : 2025-09-14 Size : 1kb User : xuchunlei

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