VHDL-FPGA-Verilog List Page 1629

VHDL-FPGA-Verilog list

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Learning-VHDL-with-example Downloaded：0: Learning VHDL, from entry to the master, including the study of books, information and case studies.
Date : 2025-09-14 Size : 27.19mb User :
mipsoc Downloaded：0: This a miniature CPU to use veriylog language program, so that the program I developed in the composition of the principles of curriculum design.
Date : 2025-09-14 Size : 7kb User : feixiang
CPU-with-VHDL-16-32 Downloaded：0: In the the quartus run 32 16-bit CPU instruction set procedures, modular design, including the MBR, BR, MR, the ACC, the MAR, the PC, the IR CU, the ROM, RAM, ALU and other modules
Date : 2025-09-14 Size : 1.58mb User :
Four-layer--double-Lift Downloaded：0: Four-story elevator intelligent system, modular design, including the elevator choices, external elevator control, elevator internal control, floor display module
Date : 2025-09-14 Size : 583kb User :
cyclecoder_decoder Downloaded：0: (7,4) cyclic code Verilog coding procedures, (7,4) cyclic code the verilog decoding procedure
Date : 2025-09-14 Size : 1kb User : 徐航
ddr2_demo Downloaded：0: the verilog source code of ddr2 control of lattice
Date : 2025-09-14 Size : 866kb User : 肖涛
four-decimal-frequency--meter Downloaded：0: Based on VHDL language design of the realization of the four decimal frequency meter
Date : 2025-09-14 Size : 35kb User : 刘海
The-traffic-lights--design Downloaded：0: Based on VHDL language implementation of traffic light control circuit design and its simulation
Date : 2025-09-14 Size : 30kb User : 刘海
Led-Display- Downloaded：0: Based on VHDL language implementation of these seven digital display decoder design and simulation
Date : 2025-09-14 Size : 36kb User : 刘海
frequency-divider Downloaded：0: Based on the numerical control language realization VHDL prescaler design and its simulation
Date : 2025-09-14 Size : 91kb User : 刘海
adding-counter- Downloaded：0: Based on VHDL language implementation of four decimal frequency meter design and its simulation
Date : 2025-09-14 Size : 34kb User : 刘海
m60BCD Downloaded：0: counter verilog configuration
Date : 2025-09-14 Size : 14kb User : 吴斐

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