VHDL-FPGA-Verilog List Page 1546

VHDL-FPGA-Verilog list

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fli Downloaded：0: --- vhdl code of d flip flop
Date : 2025-09-13 Size : 1.01mb User : perfect22
nco Downloaded：0: FPGA-based VCO oscillator input signal, the effective frequency division and any sub-frequency coefficients can be
Date : 2025-09-13 Size : 3.09mb User : zhou
Lmk1000_cfg Downloaded：0: Clock chip lmk01010 fpga configuration code
Date : 2025-09-13 Size : 1kb User : 魏源
FPGA Downloaded：0: Learning the books of the information of the FPGA development, including FPGA development Raiders
Date : 2025-09-13 Size : 10.57mb User : zbj
FPGA-2C35-EDA-bochuang Downloaded：0: UP-the CUP FPGA2C35-II platform EDA Experiment v4.3 the FPGA-eda part, the basis of the commonly used experimental code.
Date : 2025-09-13 Size : 10.74mb User :
SensorBoard Downloaded：0: Experiment of multi-functional sensor module. Rar core on the FPGA-2C35 Borch experimental box platform.
Date : 2025-09-13 Size : 12.51mb User :
BarcodeScan Downloaded：0: Bar code scanning module rar core Borch experimental box platform based on FPGA-2C35. Serial port settings: baud rate 57600bps, Parity: None Data: 8 Stop: 1
Date : 2025-09-13 Size : 1.33mb User :
miniprinter Downloaded：0: Micro printer module experiment rar core on the FPGA-2C35 Borch experimental box platform. QuartusII inside to add the uart nuclear, nios II Console constitute a man-machine interface, serial ports, and micro-printer com
Date : 2025-09-13 Size : 12.54mb User :
zigbee_sensor Downloaded：0: ZigBee wireless module experiment rar core on the FPGA-2C35 Borch experimental box platform. Add uart nuclear quartusII inside, using the serial port with the main control machine communication, access to the sensor from
Date : 2025-09-13 Size : 1.32mb User :
LEDarry Downloaded：0: LED character display, 16* the 16LED character display source code
Date : 2025-09-13 Size : 2kb User : 王亮
vlsi Downloaded：0: Reference to the 8051 MCU interrupt system, the corresponding control response function, and design an eight interrupt sources interrupt response control response system
Date : 2025-09-13 Size : 443kb User : 王天成
pinlvji Downloaded：0: In the frequency of the VHDL language, on the FPGA has been verified, the whole project file
Date : 2025-09-13 Size : 987kb User : 樊刘晓

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