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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 3.09mb
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Introduction - If you have any usage issues, please Google them yourself
FPGA-based VCO oscillator input signal, the effective frequency division and any sub-frequency coefficients can be
Packet file list
(Preview for download)
码NCO设计\码NCO测试代码\acc.v
.........\.............\altera_mf.v
.........\.............\code_nco.v
.........\.............\code_nco_test.cr.mti
.........\.............\code_nco_test.mpf
.........\.............\code_nco_test.v
.........\.............\code_nco_test.v.bak
.........\.............\cyclone_atoms.v
.........\.............\vsim.wlf
.........\.............\wave.bmp
.........\.............\.ork\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
.........\.............\....\..........................................\_primary.dat
.........\.............\....\..........................................\_primary.vhd
.........\.............\....\..............m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\verilog.asm
.........\.............\....\...............................................\_primary.dat
.........\.............\....\...............................................\_primary.vhd
.........\.............\....\...................m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\verilog.asm
.........\.............\....\...........................................................\_primary.dat
.........\.............\....\...........................................................\_primary.vhd
.........\.............\....\.c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e\verilog.asm
.........\.............\....\................................\_primary.dat
.........\.............\....\................................\_primary.vhd
.........\.............\....\.m@f_cycloneiii_pll\verilog.asm
.........\.............\....\...................\_primary.dat
.........\.............\....\...................\_primary.vhd
.........\.............\....\.....pll_reg\verilog.asm
.........\.............\....\............\_primary.dat
.........\.............\....\............\_primary.vhd
.........\.............\....\.....ram7x20_syn\verilog.asm
.........\.............\....\................\_primary.dat
.........\.............\....\................\_primary.vhd
.........\.............\....\.....stratixiii_pll\verilog.asm
.........\.............\....\...................\_primary.dat
.........\.............\....\...................\_primary.vhd
.........\.............\....\.............._pll\verilog.asm
.........\.............\....\..................\_primary.dat
.........\.............\....\..................\_primary.vhd
.........\.............\....\............_pll\verilog.asm
.........\.............\....\................\_primary.dat
.........\.............\....\................\_primary.vhd
.........\.............\....\acc\verilog.asm
.........\.............\....\...\_primary.dat
.........\.............\....\...\_primary.vhd
.........\.............\....\.lt3pram\verilog.asm
.........\.............\....\........\_primary.dat
.........\.............\....\........\_primary.vhd
.........\.............\....\...accumulate\verilog.asm
.........\.............\....\.............\_primary.dat
.........\.............\....\.............\_primary.vhd
.........\.............\....\...cam\verilog.asm
.........\.............\....\......\_primary.dat
.........\.............\....\......\_primary.vhd
.........\.............\....\....dr_rx\verilog.asm
.........\.............\....\.........\_primary.dat
.........\.............\....\.........\_primary.vhd
.........\.............\....\.......tx\verilog.asm
.........\.............\....\.........\_primary.dat
.........\.............\....\.........\_primary.vhd
.........\.............\....\....lklock\verilog.asm
.........\.............\....\..........\_primary.dat
.........\.............\....\..........\_primary.vhd
.........\.............\....\...ddio_bidir\verilog.asm
.........\.............\....\.............\_primary.dat
.........\.............\....\.............\_primary.vhd
.........\.............\....\........in\verilog.asm
.........\.............\....\..........\_primary.dat
.........\.............\....\..........\_primary.vhd
.........\.............\....\........out\verilog.asm
.........\.............\....\...........\_primary.dat
.........\.............\....\...........\_primary.vhd
.........\.............\....\....pram\veri
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