VHDL-FPGA-Verilog List Page 1541

VHDL-FPGA-Verilog list

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xyy Downloaded：0: FPGA VHDL language-based waveform generator materials and engineering code
Date : 2025-09-12 Size : 6.28mb User : panjun
61EDA_H192 Downloaded：0: IRIG-B very good verilog hdl
Date : 2025-09-12 Size : 1.76mb User : yu.zhou
fpga-cpld-tool-make Downloaded：0: the fpga debugging tools to create good practical value
Date : 2025-09-12 Size : 2.17mb User : xuxingming
AHB Downloaded：0: Better AHB Verilog realization of the master.
Date : 2025-09-12 Size : 1kb User : 冯磊
an-8-bit-left-shift-register Downloaded：0: Using VHDL to design an 8-bit left shift register. And simulation waveforms.
Date : 2025-09-12 Size : 2kb User : clementkv
FirstData_ISO8583_Global_TA_10222010_Version2010- Downloaded：0: FirstData Global TA 8513 Data
Date : 2025-09-12 Size : 3.28mb User : ph0d
1319183905_20897_FT51388_nokialcd Downloaded：0: rhis is nokia lcd rar
Date : 2025-09-12 Size : 19kb User : dedi
song Downloaded：0: This is a very interesting design, and is also a dds design of the experiment- keyboard
Date : 2025-09-12 Size : 2kb User : 张恒
freq Downloaded：0: A frequency test modules written in VHDL in Quartus under are automatically converted to the decimal number is output to the digital tube.
Date : 2025-09-12 Size : 280kb User : voldemortqq
FIFO Downloaded：0: A FIFO module in VHDL Quartus, commissioning c6000 series
Date : 2025-09-12 Size : 329kb User : voldemortqq
AD Downloaded：0: Quartus environment, the VHDL language, one of the AD conversion, 128k sampling rate analog to digital conversion
Date : 2025-09-12 Size : 322kb User : voldemortqq
counter Downloaded：0: Quartus environment verilog language of a four addend, the choice is a binary, is a good example to learn the timing
Date : 2025-09-12 Size : 223kb User : voldemortqq

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