VHDL-FPGA-Verilog List Page 1537

VHDL-FPGA-Verilog list

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counter Downloaded：0: Calculate the number of procedures Verilog xilinx
Date : 2025-09-12 Size : 108kb User : 程国苗
iic Downloaded：0: the iic communication Verilog xilinx
Date : 2025-09-12 Size : 21kb User : 程国苗
lcd Downloaded：0: the lcd 1602 Verilog ise xilinx
Date : 2025-09-12 Size : 249kb User : 程国苗
mux16 Downloaded：0: the mux multiplier Verilog ise xilinx
Date : 2025-09-12 Size : 23kb User : 程国苗
rs Downloaded：0: RS (255,239) Verilog code, through quartusII Simulation meet the design requirements, the need to take reference
Date : 2025-09-12 Size : 710kb User : 王诚
uart.main Downloaded：0: Asynchronous serial communication program with the timing of the output has already been verified
Date : 2025-09-12 Size : 3.9mb User : zenglei
bt656 Downloaded：0: the bt656 format converted to the bt601 with the YCbCr 4:2:2 format
Date : 2025-09-12 Size : 2kb User : wangda
i2c Downloaded：0: i2c configuration adv7180
Date : 2025-09-12 Size : 1kb User : wangda
ycbcr-422-to-444 Downloaded：0: YCbCr 422 to 444 format conversion
Date : 2025-09-12 Size : 1kb User : wangda
tiqutest Downloaded：0: The back of the filtered square wave signal given by the signal generator as a signal to be processed by the program can extract a pulse. Note that the square amplitude given by the signal generator is about 3.3V or so,
Date : 2025-09-12 Size : 261kb User : 张朗
fpga-mcu Downloaded：0: Uart interface 51 of microcontroller and FPGA 16-bit wide data communications, and including Bing string of data conversion.
Date : 2025-09-12 Size : 614kb User : 张朗
jishi999999 Downloaded：0: Program six counters, 000000 999999, an enable signal en enable signal en by the FPGA pin 68 access, using the signal generator to produce a square wave, en signal is 1 when the counter count for input square-wave amplit
Date : 2025-09-12 Size : 687kb User : 张朗

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