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VHDL-FPGA-Verilog list
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plljishi
Downloaded:0
Pulse counting to generate a pulse width adjustable pulse, and then as an enabling signal is sent to the counter. Test in a different phase clock count, too set the count frequency, can be found in the different phases o
Date
: 2025-09-12
Size
: 741kb
User
:
张朗
8frequency
Downloaded:0
8 digital frequency meter, proven.
Date
: 2025-09-12
Size
: 644kb
User
:
张朗
mips-verilog
Downloaded:0
verilog mips documet will show you about mips
Date
: 2025-09-12
Size
: 102kb
User
:
refreshhh
32-crc32
Downloaded:0
32 bits of data input and parallel algorithm Verilog HDL code
Date
: 2025-09-12
Size
: 11kb
User
:
cui
usb2.0
Downloaded:0
FPGA data usb2.0 port, upload the first bit machine
Date
: 2025-09-12
Size
: 690kb
User
:
张丽丽
ss868_FallingSandGame_restored
Downloaded:0
EDA ,verilog HDL
Date
: 2025-09-12
Size
: 1.72mb
User
:
pengkang
edivider
Downloaded:0
The data divided by an even number, there are test files, you can test the output signal
Date
: 2025-09-12
Size
: 945kb
User
:
张丽丽
fenpin
Downloaded:0
A multiple time divided by the program, in this way to avoid synchronized jump to the interference caused by
Date
: 2025-09-12
Size
: 12kb
User
:
张丽丽
resetdelay
Downloaded:0
This a reset delay procedures, the timing delay of the reset signal, to ensure jitter and more signals generated error
Date
: 2025-09-12
Size
: 13kb
User
:
张丽丽
LED_word
Downloaded:0
Fpga switch between the four pictures, four buttons control the display 1, 2, 3, 4, four digital
Date
: 2025-09-12
Size
: 68kb
User
:
毕无瑕
usbblock
Downloaded:0
This a usb2.0 functional modules, including a write channel read-channel, data communications in the fpga with the host computer
Date
: 2025-09-12
Size
: 14kb
User
:
张丽丽
designing-of-FIR-filer-based-on-FPGA
Downloaded:0
designing of FIR filer based on FPGA
Date
: 2025-09-12
Size
: 4kb
User
:
董红柏
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.31
.32
.33
.34
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1536
.37
.38
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.40
.41
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4310
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