VHDL-FPGA-Verilog List Page 1531

VHDL-FPGA-Verilog list

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spartan3e Downloaded：0: this source is pin ucf for spartan 3e
Date : 2025-09-12 Size : 2kb User : rita
carnegie-mellon-verilog Downloaded：0: verilog course handouts to explain the detailed and useful information for beginners FPGA.
Date : 2025-09-12 Size : 229kb User :
Digital-baseband-system- Downloaded：0: Digital baseband system modeling and design
Date : 2025-09-12 Size : 381kb User : 崔小久
nios Downloaded：0: The soft-core NIOS to do based on the DE2, including PLL, SDRAM modules, you can run the basic program
Date : 2025-09-12 Size : 15.05mb User : judeliu
FIBER_LOC_C Downloaded：0: CPU SYSTEM LOGIC CONTROL
Date : 2025-09-12 Size : 2kb User : wanglei
wannianli3 Downloaded：0: a calender based on VHDL,show numbers by Nixie tube
Date : 2025-09-12 Size : 2kb User : nightknight
Count-display-circuit-design(VHDL) Downloaded：0: VHDL language to count the display circuit. The design output for display circuit 3 BCD count. Consists of three modules: the decimal counter (BCD_CNT), time division bus switching circuit (SCAN) and seven-segment displa
Date : 2025-09-12 Size : 45kb User : hhsyla
shuokongfenpin Downloaded：0: It s important foe you!
Date : 2025-09-12 Size : 21kb User : 叶特丽
ADC0809caiyang Downloaded：0: The A/D sampling circuit. eda experimental principle and schematic detailed instructions
Date : 2025-09-12 Size : 18kb User : 叶特丽
banjiaqisheji Downloaded：0: Half adder design. Useful experimental operation report. Detailed steps in EDA
Date : 2025-09-12 Size : 635kb User : 叶特丽
uart_verilog Downloaded：0: VERILOG a serial port to receive example, can receive a single byte, appropriate to add a small amount of code can be any byte receive.
Date : 2025-09-12 Size : 74kb User : 毛毛雨0410
ECE-SOPC_SDRAM Downloaded：0: The FPGA the NIOS II to SDRAM read and write operations, experimental verification is passed, can be freely used.
Date : 2025-09-12 Size : 8.24mb User : 毛毛雨0410

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