VHDL-FPGA-Verilog List Page 1548

VHDL-FPGA-Verilog list

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kt3tuo Downloaded：0: Multi-functional digital clock system (hierarchical design) in the FPGA-based development features include: timekeeping, school Calibration of 6-18 hours to control lighting
Date : 2025-09-13 Size : 560kb User : cynthia
exp_cnt_xuehao365_7seg Downloaded：0: Counter digital tube three decimal exp_cnt_xuehao365_7seg. VHD for top level file
Date : 2025-09-13 Size : 3kb User : zone
timecontrol Downloaded：0: using verilog to generate bakema and write series datas for PLL conifgure.
Date : 2025-09-13 Size : 1kb User : D.eason
RTThread_uart1 Downloaded：0: RTSTREAD functions: the use of general-purpose timers to achieve timing plus a
Date : 2025-09-13 Size : 5.47mb User : acq
DE2_70_D5M_LTM_after_SDRAM Downloaded：0: SDRAM as a buffer, the captured image to display LTM
Date : 2025-09-13 Size : 194kb User : 陈英文
20bitBINtoBCD Downloaded：0: 50MHz clock and drive six digital tube display increment count
Date : 2025-09-13 Size : 3kb User : 黎勇
led_key_beep Downloaded：0: Independent keys of the input four output four separate LED and a buzzer. Key is pressed, the corresponding LED variable, while the buzzer sounds, release the button, the corresponding LED off, does not sound buzzer. Buz
Date : 2025-09-13 Size : 2kb User : lcl
fpxz Downloaded：0: Frequency selection system. the inclk0 side input 25MHz signal, multiplier by altpll at 400MHz signal C0-ended output, demand not the same as their own to change the parameters of frequency multiplier. The divider clkdiv
Date : 2025-09-13 Size : 339kb User : lcl
pinlvji_LCD1602 Downloaded：0: Has been a complete VHDL program measurement and verification, measurement range from 1Hz to 1GHz frequency counter can be used as a counter LCD1602 displays frequency value, the four separate buttons can control the out
Date : 2025-09-13 Size : 1.05mb User : lcl
uartest Downloaded：0: uart transmit module test, including the baud rate conversion and the uart send module. The system clock is 50M.
Date : 2025-09-13 Size : 493kb User : 蒋沪生
cide_c2 Downloaded：0: The Ethernet chips DM9000A test, the program is configured DM9000a, allows the chip to complete the Ethernet port to send data.
Date : 2025-09-13 Size : 9.15mb User : 蒋沪生
klt1 Downloaded：0: the klt algorithm of the fpga implementation, altera company s development environment.
Date : 2025-09-13 Size : 361kb User : 蒋沪生

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